A Chopper-Stabilized Amplifier with a Relaxed Fill-In Technique and 22.6pA Input Current

In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is mainly due to finite amplifier bandwidth, which causes signal-dependent output spikes at the chopping transitions. Such chopper-induced IMD can be mitigated by the fill-in technique, which involves ping...

A BJT-Based CMOS Temperature Sensor with Duty-Cycle-Modulated Output and ±0.5°C (3σ) Inaccuracy from -40 °c to 125 °c

This brief presents a 0.65% relative inaccuracy CMOS temperature sensor with a duty-cycle-modulated (DCM) output. It uses a BJT-based front-end to generate a proportional to absolute temperature voltage (V_{PTAT}) and a complementary to absolute temperature voltage (V_{CTAT}), which are then modulated to a digital-friendly duty-cycle output....

Know when to listen: SDN-based protocols for directed IoT networks

Low-power wireless networks are an integral part of the Internet of Things, composed of resource-constrained devices harvesting ambient information.<br/>The appearance of unidirectional links is characteristic of low power wireless networking due to physical effects, device heterogeneity and manufacturing imperfections.<br/>Despite the...

An Accurate BJT-Based CMOS Temperature Sensor With Duty-Cycle-Modulated Output

This paper describes the design of a precision bipolar junction transistor based temperature sensor implemented in standard 0.7-μmCMOS technology. It employs substrate p-n-ps as sensing elements,which makes it insensitive<br/>to the effects of mechanical (packaging) stress and facilitates the use of low-cost packaging technologies. The sensor...

A Sampled Voltage Reference

A sampled voltage reference aims to achieve both low-power and low-noise by storing the output of a voltage reference on a capacitor for a long time. This allows the reference to be switched off during the hold period, which leads to lower average power. At the same time, all the voltage reference's noise is pushed down into a bandwidth...

Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs

This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This is the first-ever Duty-Cycled PLL (DCPLL) that is designed with an LC oscillator and brings down the noise record for DCPLLs by more than 1 order of magnitude. Due to the special...

Network Lifetime Analysis of Data Collection Protocols

When a sensor network is deployed, we fundamentally care about three main outcomes: to obtain as much data as possible (high delivery rate), to obtain data as fast as possible (low latency), and to obtain data for as long as possible (long lifetime). This last metric, called network lifetime, is of great importance and has been widely...

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

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