Operating system support for a dynamically reconfigurable VLIW processor

The ρ-VEX is a dynamically reconfigurable VLIW processor, developed at TU Delft, which is capable of extracting large amounts of parallelism from applications running on it. However, without a dedicated software layer to dictate the reconfigurations, the ρ-VEX has to depend on another processor to carry out its reconfigurations meaningfully....

Optimizing Multicore System Performance Using Dynamically Reconfigurable Architectures on FPGAs

Processor architecture is continuously evolving. As the trend predicted by Moore's law is nearing its end, the focus of designing processors has shifted from high-frequency single-core systems to the medium frequency multicore system to a relatively lower frequency many-cores system, in the hope of extracting more performance while keeping power...

Targeting static and dynamic workloads with a reconfigurable VLIW processor

Embedded systems range from very simple devices, such as a digital watch, to highly complex systems such as smartphones. In these complex devices, an increasing number of applications need to be executed on a computing platform. Moreover, the number of applications (or programs) usually exceeds the number of processors found on such platforms....

A Dynamically Reconfigurable VLIW Processor and Cache Design with Precise Trap and Debug Support

This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...