Searched for: subject:"gates"
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document
Chen, T. (author), Ishihara, R. (author), Beenakker, K. (author)
In this article, we investigated the high quality SiO2 deposited at 80°C by inductively coupled plasma enhanced chemical vapor deposition (CVD). The interface trap density of 1.48×1010 cm?2 eV?1 and breakdown voltage of 5.6 MV/cm were realized successfully despite the low deposition temperature. Thin film transistors (TFTs) have been fabricated...
journal article 2010
document
Yan, F. (author), Migliorato, P. (author), Hong, Y. (author), Rana, V. (author), Ishihara, R. (author), Hiroshima, Y. (author), Abe, D. (author), Inoue, S. (author), Shimoda, T. (author)
The transient drain current of the single-grain silicon thin-film transistor with gate oxide deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition has been measured by applying a square signal on the gate and a constant low voltage between source and drain. Switch-on undershoot current has been observed, which can...
journal article 2005