Optimal Control Allocation on Over-Actuated Vehicles

Modern passenger vehicles are equipped with an increasing number of actuators that may be used to actively control the lateral and longitudinal dynamics of the vehicle. During limit-handling situations, proper coordination of all the available actuators by the vehicle stability control (VSC) can lead to improved overall control authority, which...

Porting Linux to the rVEX reconfigurable VLIW softcore

This thesis describes the design and implementation of an FPGA-based hardware platform based on the rVEX VLIW softcore and the adaption of a Linux 2.0 no_mmu kernel to run on that platform. The rVEX is a runtime reconfigurable VLIW softcore processor. It supports various configurations that allow programs to run faster or more efficient. The...

Iterative Instruction Scheduling for a VLIW Processor

Instruction scheduling aims to reorder instructions in such a way that it covers the delay between an instruction and its dependent successor(s). As a result, the length of schedules are shortened while the processor utilisation increases. This is accomplished by exploiting Instruction Level Parallelism (ILP). The rearrangements made by...

Porting GCC to a Clustered VLIW Processor

A clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this...

Compile time aanalysis for hardware transactional memory architectures

Transactional Memory is a parallel programming paradigm in which tasks are executed, in forms of transactions, concurrently by different resources in a system and resolve conflicts between them at run-time. Conflicts, caused by data dependencies, result in aborts and restarts of transactions, thus, degrading the performance of the system. In...

A Memory Access and Operator Usage Pro?ler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study

As recon?gurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS...

Porting the GCC Compiler to a VLIW Vector Processor

Applications run on embedded DSPs become increasingly complex, while the demands on speed and power continue to grow. One method of meeting these demands is to move some of the processor complexity from hardware to the compiler. This increases the importance of the role of the compiler. This thesis describes how we ported the Gnu Compiler...