A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...

A 33-ppm/°C 240-nW 40-nm CMOS Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased Σ Δ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter,...

A 0.7-V 0.43-pJ/cycle Wakeup Timer based on a Bang-bang Digital-Intensive frequency-Locked-Loop for IoT Applications

A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the...