A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC

This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm HPC for a GHz sampling Σ∆ modulator.<br/>In the earlier design, the size of the pMOS in an inverter was found to be nine times larger than the nMOS which is not practical to obtain a...