Ultra-Low Power On-Chip Oscillator: A 0.9-V 1.039-MHz 20.51-fJ/cycle oscillator in 28-nm CMOS with rail-to-rail output swing

A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-thermal Drain Voltage Stabilization and Frequency Locked Loop

A 6.4 nW 1.7% relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming and increases the accuracy of the sensor. A combination of the current...

A 60 mV Input Voltage, Process Tolerant Start-Up System for Thermoelectric Energy Harvesting

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring <br/>oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra...

An Ultra-Low Power Capacitive Readout Circuit for Wake-on-Touch Applications

Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather...

Edge-prediction DTC and Clock-gating TDC Design for Ultra Low Power All Digital PLL

A Low Power 10-bit SAR ADC in a 45nm CMOS process

In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the conventional 2^N , thus decreasing the DAC area and the DAC...

Design of a fully integrated CMOS highly temperature stable frequency reference

A new fully integrated frequency reference has been designed, fabricated and measured. The goal of the design procedure has been high stability of the frequency over temperature variations. This should be achieved using a CMOS technology without MEMS and crystals, while being restricted by a very low power budget. The frequency is designed based...

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

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