Optimizing the Cost and Performance for Batch jobs on HPC by Utilizing Swap Space

High Performance Computing (HPC) facilities play a crucial role in acceler- ating Electronic Design Automation (EDA) procedures at NXP Semiconduct- ors. The increasing number of job requests and workloads has led to a surge in memory demand, which is a costly resource. To address this, we leverage memory swap space on disk as a more affordable...

To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration

As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep...

Typesafe by Definition for Languages with Explicit Deallocation

A definitional interpreter is an interpreter which uses the semantics of its own host language to define those of its object language. Traditionally, a seperate type safety proof is used for such an interpreter. Using a "typesafe-by-construction" approach, where the typesafety is proven by expressing the type system of the object language in the...

Binary Variable-to-Fixed Length Balancing Scheme with Simple Encoding/Decoding

We present a systematic variable-to-fixed (VF) length scheme encoding binary information sequences into binary balanced sequences. The redundancy of the proposed scheme is larger than the redundancy of the best fixed-to-fixed (FF) length schemes in case of long codes, but it is smaller in case of short codes. The biggest advantage comes from...