Searched for: subject%3A%22phase%255C-locked%255C+loop%22
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Gao, Z. (author)
Reducing power consumption is becoming increasingly important for the sustainability of the communication industry because it is expected to consume a significant portion of the global electricity in the face of the exponentially increasing demands on the volume and rate of data transmission. As the scope narrows to the individual wireless...
doctoral thesis 2023
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Gong, J. (author)
Quantum computers have gained widespread interest from both industry and academia in the last decade as they are very promising for solving problems intractable by classical computers. However, there is a limited number of qubits in current quantum processors, which impedes the practical applications of a quantum computer. To increase the number...
doctoral thesis 2023
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Gao, Z. (author), He, J. (author), Fritz, Martin (author), Shen, Y. (author), Zong, Z. (author), Spalink, Gerd (author), Alavi, S.M. (author), Staszewski, R.B. (author), Babaie, M. (author)
This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...
journal article 2023
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Gong, J. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)
This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated...
journal article 2023
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Gurbaxani, Rishabh (author)
Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered...
master thesis 2022
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Chen, Y. (author)
The scaling of CMOS technology in deep submicron process nodes is accompanied by the integration of more and more functional blocks of a system, whether digital or analog/RF, onto the same chip (i.e., system-onchip, SoC). These blocks would also place different requirements on their power supplies. To provide various static or dynamically...
doctoral thesis 2022
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Herrejón-Pintor, Gilberto A. (author), Melgoza-Vázquez, Enrique (author), de Jesus Chavez, Jose (author)
The controls of most power electronic inverters connected to an electrical power system (EPS) rely on the precise determination of the voltage magnitude, frequency, and phase angle at the point of common coupling. One of the most widely used approaches for measuring these quantities is the phase-locked loop (PLL); however, the precision of this...
journal article 2022
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Gong, J. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses...
journal article 2022
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Chen, Y. (author), Gong, J. (author), Staszewski, R.B. (author), Babaie, M. (author)
In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...
journal article 2022
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Li, Chao Chieh (author), Yuan, Min Shueh (author), Liao, Chia Chun (author), Chang, Chih Hsien (author), Lin, Yu Tso (author), Tsai, Tsung Hsien (author), Huang, Tien Chien (author), Liao, Hsien Yuan (author), Staszewski, R.B. (author)
In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched...
journal article 2021
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Liu, Bangan (author), Zhang, Yuncheng (author), Qiu, Junjun (author), Ngo, Huy Cu (author), Deng, Wei (author), Nakata, Kengo (author), Yoshioka, Toru (author), Emmei, Jun (author), Pang, Jian (author), Someya, T. (author)
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...
journal article 2021
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Pimenta, Matheus (author), Gürleyük, C. (author), Walsh, Paul (author), O’Keeffe, Daniel (author), Babaie, M. (author), Makinwa, K.A.A. (author)
This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a...
journal article 2021
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Beloqui Larumbe, L. (author), Qin, Z. (author), Wang, L. (author), Bauer, P. (author)
This article presents a small-signal model for power-electronics converters that use a typical control structure in wind energy applications: the double synchronous reference frame current control. The article considers the presence of unbalanced currents and voltages, and analyzes their impact on the frequency couplings of the converter. In...
journal article 2021
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Verschuren, Ties (author)
In pursuit of extremely sensitive sensors, the dimensions of these sensors get smaller and smaller. Small scale resonators are commonly used as sensors by relating changes in the dynamic behaviour to a sensed quantity. Conventionally, the dynamics used for sensing are in the linear regime. But at smaller scales the dynamic range of the linear...
master thesis 2020
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Manzaneque Garcia, T. (author), Steeneken, P.G. (author), Alijani, F. (author), Ghatkesar, M.K. (author)
Resonant sensors determine a sensed parameter by measuring the resonance frequency of a resonator. For fast continuous sensing, it is desirable to operate resonant sensors in a closed-loop configuration, where a feedback loop ensures that the resonator is always actuated near its resonance frequency, so that the precision is maximized even in...
journal article 2020
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Beloqui Larumbe, L. (author), Qin, Z. (author), Bauer, P. (author)
A voltage imbalance at the AC terminals of a three-phase inverter creates a ripple in the power signal on the DC side. In order to minimize this ripple, several techniques can be applied, in which a double Synchronous Reference Frame (SRF) current control structure is very typical. In this approach, both the positive and negative sequence...
conference paper 2020
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Chen, Peng (author), Zhang, Feifei (author), Zong, Z. (author), Hu, Suoping (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold...
journal article 2019
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Kremers, Arjen (author)
Offshore wind power plants are subject to adverse electrical conditions that are more severe than onshore cases, due to the long cable connection to the shore. Among these conditions are amplified voltage distortion at (inter)harmonic frequencies, as well as stability issues. An important aspect of wind turbine generator control is the phase...
master thesis 2019
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Does, Luc (author)
In this thesis, the design and implementation of an improved current controller for grid-tied converters is discussed. Using this improved current controller, a power factor correction test platform achieves practically zero AC and DC error in steady-state. The power factor corrector accomplishes this by utilizing the parallel combination of a...
master thesis 2019
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Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f <sup>3</sup> ) and thermal (1/f <sup>2</sup> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...
journal article 2019
Searched for: subject%3A%22phase%255C-locked%255C+loop%22
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