Searched for: subject%3A%22phase%255C-locked%255C%2Bloop%255C%2B%255C%2528PLL%255C%2529%22
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Gao, Z. (author)
Reducing power consumption is becoming increasingly important for the sustainability of the communication industry because it is expected to consume a significant portion of the global electricity in the face of the exponentially increasing demands on the volume and rate of data transmission. As the scope narrows to the individual wireless...
doctoral thesis 2023
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Gao, Z. (author), He, J. (author), Fritz, Martin (author), Shen, Y. (author), Zong, Z. (author), Spalink, Gerd (author), Alavi, S.M. (author), Staszewski, R.B. (author), Babaie, M. (author)
This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...
journal article 2023
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Gong, J. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)
This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated...
journal article 2023
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Beloqui Larumbe, L. (author), Qin, Z. (author), Wang, L. (author), Bauer, P. (author)
This article presents a small-signal model for power-electronics converters that use a typical control structure in wind energy applications: the double synchronous reference frame current control. The article considers the presence of unbalanced currents and voltages, and analyzes their impact on the frequency couplings of the converter. In...
journal article 2021
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Liu, Bangan (author), Zhang, Yuncheng (author), Qiu, Junjun (author), Ngo, Huy Cu (author), Deng, Wei (author), Nakata, Kengo (author), Yoshioka, Toru (author), Emmei, Jun (author), Pang, Jian (author), Someya, T. (author)
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...
journal article 2021
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Pimenta, Matheus (author), Gürleyük, C. (author), Walsh, Paul (author), O’Keeffe, Daniel (author), Babaie, M. (author), Makinwa, K.A.A. (author)
This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a...
journal article 2021
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Chen, Peng (author), Zhang, Feifei (author), Zong, Z. (author), Hu, Suoping (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold...
journal article 2019
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Zhuang, J. (author), Staszewski, R.B. (author)
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The natural predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing...
journal article 2014
Searched for: subject%3A%22phase%255C-locked%255C%2Bloop%255C%2B%255C%2528PLL%255C%2529%22
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