A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to V<sub>DD<...

A Low Power System-on-Chip with Memory Stacked on Top of Logic

This work introduces a low-power Cortex-M0+ based computing platform for battery-powered, embedded applications. Voltage stacking is used to save power by recycling charge through a power domain between 0V and Vdd, and a power domain stacked on top of it between Vdd and 2Vdd. The technique enables connecting chips of the future directly to the...