Searched for: subject:"%5C%3F%5C-VEX"
(1 - 13 of 13)
document
van Bremen, Lennart (author)
The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.
A fully automatic scripted flow is described, constructing an...
master thesis 2017
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Yanik, K.I.M. (author)
The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...
master thesis 2016
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Heij, R.W. (author)
In this work a fast and efficient implementation of a Field Programmable Gate Array (FPGA) based, fixed hardware, streaming multiprocessor architecture for low latency medical image processing is introduced. The design of this computation fabric is based on the ρ-VEX Very Long Instruction Word (VLIW) softcore processor and is in influenced by...
master thesis 2016
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Van Straten, J. (author)
This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...
student report 2016
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Johansen, J. (author)
The ?-VEX is a run-time reconfigurable Very Long Instruction Word (VLIW) processor. This unique processor allows separation of its issue lanes to form independently operating processing cores. Switching between these configuration during run-time allows optimizing the platform for the task(s) it is performing. Porting an Operating System (OS) to...
master thesis 2016
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Van der Wijst, H. (author)
In recent years the use of co-processors to accelerate specific tasks is becoming more common. To simplify the use of these accelerators in software, the OpenCL framework has been developed. This framework provides programs a cross-platform interface for using accelerators. The ?-VEX processor is a run-time reconfigurable VLIW processor. It...
master thesis 2015
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Meun, K. (author)
Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a...
master thesis 2015
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Daverveldt, M.A.F.M. (author)
This thesis describes the development of an LLVM-based compiler for the ?-VEX processor. The ?-VEX processor is a runtime re- configurable VLIW processor. Currently, two compilers exist that target the ?-VEX processor: a HP-VEX compiler and a GCC-based compiler. We show that both compilers have disadvantages that are very dif- ficult to fix....
master thesis 2014
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Purba, M.S.B. (author), Yigit, E. (author), Regeer, A.J.J. (author)
Deze scriptie beschrijft het ontwerp van een embedded systeem dat de kenmerkende eigenschappen uit de afbeelding van een vingerafdruk haalt. Het betreft een hardware/software codesign, waarbij een VLIW-processor als accelerator is gebruikt.
bachelor thesis 2011
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Van den Broeke, G. (author), Mul, D.P.N. (author)
Deze scriptie betreft een onderzoek naar het versnellen van een JPEG-decoder in een embedded systeem. Hierbij wordt de ?-VEX VLIW-processor als accelerator gebruikt. Onderzocht wordt hoe de hardware en software aan elkaar kunnen worden aangepast om de applicatie zo snel mogelijk uit te voeren.
bachelor thesis 2011
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Kong, Q. (author)
In this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (interrupt latency). On the other hand, due to...
master thesis 2011
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Seedorf, R.A.E. (author)
The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...
master thesis 2010
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Van As, T. (author)
Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and...
master thesis 2008
Searched for: subject:"%5C%3F%5C-VEX"
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