This article presents an application-specific integrated circuit (ASIC) for catheter-based 3-D ultrasound imaging probes. The pitch-matched design implements a comprehensive architecture with high-voltage (HV) transmitters, analog front ends, hybrid beamforming analog-To-digital converters (ADCs), and data transmission to the imaging system. To reduce the number of cables in the catheter while maintaining a small footprint per element, transmission (TX) beamforming is realized on the chip with a combination of a shift register (SR) and a row/column (R/C) approach. To explore an additional cable-count reduction in the receiver part of the design, a channel with a combination of time-division multiplexing (TDM), subarray beamforming, and multi-level pulse amplitude modulation (PAM) data transmission is also included. This achieves an 18-fold cable-count reduction and minimizes the power consumption in the catheter by a load modulation (LM) cable driver. It is further explored how common-mode interference can limit beamforming gain and a strategy to reduce its impact with local regulators is discussed. The chip was fabricated in TSMC 0.18-m HV BCD technology and a 2-D PZT transducer matrix of 16 × 18 elements with a pitch of 160 m and a center frequency of 6 MHz was manufactured on the chip. The system can generate all required TX patterns at up to 30 V, provides quick settling after the TX phase, and has an reception (RX) power consumption of only 1.12 mW/element. The functionality and operation of up to 1000 volumes/s have been demonstrated in electrical and acoustic imaging experiments.

In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The integration challenge is met by a hybrid analog-to-digital converter (ADC), combining an efficient charge-sharing successive approximation register (SAR) first stage and a compact single-slope (SS) second stage. Application in large ultrasound imaging arrays is facilitated by directly interfacing the ADC with a charge-domain subarray beamformer, locally calibrating interstage gain errors and generating the SAR reference using a power-efficient local reference generator. Additional hardware-sharing between neighboring channels ultimately leads to the lowest reported area and power consumption across miniature ultrasound probe ADCs. A pitch-matched design is further enabled by an efficient split between the core circuitry and a periphery block, the latter including a datalink performing clock data recovery (CDR) and time-division multiplexing (TDM), which leads to a 12-fold total channel count reduction. A prototype of $8{\times }9$ elements was fabricated in a TSMC 0.18- $\mu \text{m}$ HV BCD technology and a 2-D PZT transducer matrix with a pitch of $160 \mu \text{m}$ , and a center frequency of 6 MHz was manufactured on the chip. The imaging device operates at up to 1000 volumes/s, generates 65-V transmit pulses, and has a receive power consumption of only 1.23 mW/element. The functionality has been demonstrated electrically as well as in acoustic and imaging experiments.

Intra-cardiac echography (ICE) probes (Fig. 32.2.1) are widely used in electrophysiology for their good procedure guidance and relatively safe application. ASICs are increasingly employed in these miniature probes to enhance signal quality and reduce the number of connections needed in mm-diameter catheters [1]-[5]. 3D visualization in real-time is additionally enabled by 2D transducer arrays with, for each transducer element, a high-voltage (HV) transmit (TX) part, to generate acoustic pulses of sufficient pressure, and a receive (RX) path, to process the resulting echoes. To achieve the required reduction in RX channels, micro-beamforming (BF), which merges the signals from a subarray using a delay-and-sum operation, has been shown to be an effective solution [3], [4]. However, due to the frame-rate reduction that is associated with BF, these designs cannot serve emerging high-frame-rate imaging modes (1000 volumes/s) like 3D blood-flow and elastography imaging. In-probe digitization has recently been investigated to provide further channel-count reduction, make data transmission more robust, and enable pre-processing in the probe [1]-[3]. However, these earlier designs have either no TX functionality [2], [3] or only low-voltage (LV) TX [1] integrated. Combining BF and digitization with area-hungry HV transmitters in a pitch-matched scalable fashion while supporting high-frame-rate imaging remains an unmet challenge. The work presented in this paper meets this target, enabled by a hybrid ADC, the small die size of which allows for co-integration with 65V element-level pulsers.

This article presents a compact analog front-end (AFE) circuit for ultrasound receivers with linear-in-dB continuous gain control for time-gain compensation (TGC). The AFE consists of two variable-gain stages, both of which employ a novel complementary current-steering network (CCSN) as the interpolator to realize continuously variable gain. The first stage is a trans-impedance amplifier (TIA) with a hardware-sharing inverter-based input stage to save power and area. The TIA's output couples capacitively to the second stage, which is a class-AB current amplifier (CA). The AFE is integrated into an application-specific integrated circuit (ASIC) in a 180-nm high-voltage BCD technology and assembled with a 100 μm-pitch PZT transducer array of 8 × 8 elements. Both electrical and acoustic measurements show that the AFE achieves a linear-in-dB gain error below ±0.4 dB within a 36-dB gain range, which is > 2 × better than the prior art. Per channel, the AFE occupies 0.025 mm2 area, consumes 0.8 mW power, and achieves an input-referred noise density of 1.31 pA/√Hz.

This article presents an application-specific integrated circuit (ASIC) designed for intra-vascular ultrasound imaging that interfaces 64 piezoelectric transducer elements to an imaging system using a single micro-coaxial cable. Thus, it allows a single-element transducer to be replaced by a transducer array to enable 3-D imaging. The 1.5-mm-diameter ASIC is intended to be mounted at the tip of a catheter, directly integrated with a 2-D array of piezoelectric transducer elements. For each of these elements, the ASIC contains a high-voltage (HV) switch, allowing the elements to transmit an acoustic wave in response to an HV pulse generated by the imaging system. A low-noise amplifier then amplifies the resulting echo signals and relays them as a signal current to the imaging system, while the same cable provides a 3-V supply. Element selection and other settings can be programmed by modulating configuration data on the supply, thus enabling full synthetic aperture imaging. An integrated element test mode measures the element capacitance to detect bad connections to the transducer elements. The ASIC has been fabricated in a 0.18- μm HV CMOS technology and consumes only 6 mW in receive. Electrical measurements show correct switching of 30-V transmit pulses and a receive amplification with a 71-dB dynamic range, including 12 dB of programmable gain over a 3-dB bandwidth of 21 MHz. The functionality of the ASIC has been successfully demonstrated in a 3-D imaging experiment.

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmis-sions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.

This article presents a low-noise transimpedance amplifier (TIA) designed for miniature ultrasound probes. It provides continuously variable gain to compensate for the time-dependent attenuation of the received echo signal. This time-gain compensation (TGC) compresses the echo-signal dynamic range (DR) while avoiding imaging artifacts associated with discrete gain steps. Embedding the TGC function in the TIA reduces the output DR, saving power compared to prior solutions that apply TGC after the low-noise amplifier. The TIA employs a capacitive ladder feedback network and a current-steering circuit to obtain a linear-in-dB gain range of 37 dB. A variable-gain loop amplifier based on current-reuse stages maintains constant bandwidth in a power-efficient manner. The TIA has been integrated in a 64-channel ultrasound transceiver application-specific integrated circuit (ASIC) in a 180-nm BCDMOS process and occupies a die area of 0.12 mm2. It achieves a gain error below ±1 dB and a 1.7 pA/ √ Hz noise floor and consumes 5.2 mW from a ±0.9 V supply. B-mode images of a tissue-mimicking phantom are presented that show the benefits of the TGC scheme.

This article presents a fully integrated 64-channel programmable ultrasound transmit beamformer for catheter-based ultrasound probes, designed to interface with a capacitive micro-machined ultrasound transducer (CMUT) array. The chip is equipped with programmable high-voltage (HV) pulsers that can generate ±30-V return-to-zero (RZ) and non-RZ pulses. The pulsers employ a compact back-to-back isolating HV switch topology that employs HV floating-gate drivers with only one HV MOS transistor each. Further die-size reduction is achieved by using the RZ switches also as the transmit/receive (T/R) needed to pass received echo signals to low-voltage receive circuitry. On-chip digital logic clocked at 200 MHz allows the pulse timing to be programmed with a resolution of 5 ns, while supporting pulses of 1 cycle up to 63 cycles. The chip has been implemented in 0.18-μm HV Bipolar-CMOS-DMOS (BCD) technology and occupies an area of 1.8 mm ×16.5 mm, suitable for integration into an 8-F catheter. Each pulser with embedded T/R switch and digital logic occupies only 0.167 mm2. The pulser successfully drives an 18-pF transducer capacitance at pulse frequencies up to 9 MHz. The T/R switch has a measured ON-resistance of ~180Ω. The acoustic results obtained in combination with a 7.5-MHz 64-element CMUT array demonstrate the ability to generate steered and focused acoustic beams.

Intravascular ultrasound is an imaging modality used to visualize atherosclerosis from within the inner lumen of human arteries. Complex lesions like chronic total occlusions require forward-looking intravascular ultrasound (FL-IVUS), instead of the conventional side-looking geometry. Volumetric imaging can be achieved with 2D array transducers, which present major challenges in reducing cable count and device integration. In this work we present an 80-element lead zirconium titanate (PZT) matrix ultrasound transducer for FL-IVUS imaging with a front-end application-specific integrated circuit (ASIC) requiring only 4 cables. After investigating optimal transducer designs we fabricated the matrix transducer consisting of 16 transmit (TX) and 64 receive (RX) elements arranged on top of an ASIC having an outer diameter of 1.5 mm and a central hole of 0.5 mm for a guidewire. We modeled the transducer using finite element analysis and compared the simulation results to the values obtained through acoustic measurements. The TX elements showed uniform behavior with a center frequency of 14 MHz, a -3 dB bandwidth of 44 % and a transmit sensitivity of 0.4 kPa/V at 6 mm. The RX elements showed center frequency and bandwidth similar to the TX elements, with an estimated receive sensitivity of 3.7 μV/Pa. We successfully acquired a 3D FL image of three spherical reflectors in water using delay-and-sum beamforming and the coherence factor method. Full synthetic aperture acquisition can be achieved with frame rates on the order of 100 Hz. The acoustic characterization and the initial imaging results show the potential of the proposed transducer to achieve 3D FL-IVUS imaging.

This paper presents an area- and power-efficient application-specified integrated circuit (ASIC) for 3-D forward-looking intravascular ultrasound imaging. The ASIC is intended to be mounted at the tip of a catheter, and has a circular active area with a diameter of 1.5 mm on the top of which a 2-D array of piezoelectric transducer elements is integrated. It requires only four micro-coaxial cables to interface 64 receive (RX) elements and 16 transmit (TX) elements with an imaging system. To do so, it routes high-voltage (HV) pulses generated by the system to selected TX elements using compact HV switch circuits, digitizes the resulting echo signal received by a selected RX element locally, and employs an energy-efficient load-modulation datalink to return the digitized echo signal to the system in a robust manner. A multi-functional command line provides the required sampling clock, configuration data, and supply voltage for the HV switches. The ASIC has been realized in a 0.18-μm HV CMOS technology and consumes only 9.1 mW. Electrical measurements show 28-V HV switching and RX digitization with a 16-MHz bandwidth and 53-dB dynamic range. Acoustical measurements demonstrate successful pulse transmission and reception. Finally, a 3-D ultrasound image of a three-needle phantom is generated to demonstrate the imaging capability.

This paper presents a front-end application-specified integrated circuit (ASIC) integrated with a 2-D PZT matrix transducer that enables in-probe digitization with acceptable power dissipation for the next-generation endoscopic and catheter-based 3-D ultrasound imaging systems. To achieve power-efficient massively parallel analog-to-digital conversion (ADC) in a 2-D array, a 10-bit 30 MS/s beamforming ADC that merges the subarray beamforming and digitization functions in the charge domain is proposed. It eliminates the need for costly intermediate buffers, thus significantly reducing both power consumption and silicon area. Self-calibrated charge references are implemented in each subarray to further optimize the system-level power efficiency. High-speed datalinks are employed in combination with the subarray beamforming scheme to realize a 36-fold channel-count reduction and an aggregate output data rate of 6 Gb/s for a prototype receive array of 24 x 6 elements. The ASIC achieves a record power efficiency of 0.91 mW/element during receive. Its functionality has been demonstrated in both electrical and acoustic imaging experiments.

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm² ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

This paper presents a front-end ASIC for forward-looking intravascular ultrasound (IVUS) imaging. The ASIC is intended to be mounted at the tip of a catheter and can interface a total of 80 piezo-electric transducer elements with an imaging systems using only 4 cables, thus significantly reducing the system complexity compared to the prior art. It is capable of switching high-voltage transmit pulses to 16 transmit elements, and capturing the resulting echo signals using 64 multiplexed receive elements. The ASIC digitizes the received signals locally, providing more robust communication than prior analog approaches. Measurements show that the ASIC effectively switches transmit pulses up to 30 V, and digitizes echo signals with a bandwidth of 16 MHz, while consuming only 10 mW. Acoustic measurements in combination with a prototype transducer array demonstrate pulse transmission and reception. Finally, a B-mode image of a needle phantom demonstrates the imaging capability.