This thesis presents our investigations on how to efficiently utilize on-chip wires to improve network performance in reconfigurable hardware. A fieldprogrammable gate array (FPGA), as a key component in a modern reconfigurable platform, accommodates many-millions of wires and the on-demand reconfigurability is realized using this abundance of wires. Modern FPGAs become computationally powerful as hardware IP (intellectual property) modules such as embedded memories, processor cores, and DSP modules are accommodated. However, the performance and the cost of the inter-IP communication remains a main challenge. We meet this challenge in two aspects. First, conventional general-purpose on-chip networks suffer from high area cost when they are mapped onto the reconfigurable fabric. To reduce the area cost, we present a topology customization technique for a given set of applications. Specifically, we present an application-specific crossbar switch, crossbar schedulers, point-to-point interconnects, and circuit-switched networks-on-chip (NoCs) that reside on top of a reconfigurable fabric. As a result, by establishing only the necessary network resources, our customized interconnects provide significantly reduced cost compared to general-purpose on-chip networks. Second, while the reconfigurability is a key benefit in FPGAs, it is traded off by decreased performance and increased cost. This is mainly because of the bit-level reconfigurable interconnects. To increase performance and reduce cost, we propose to replace the bit-level reconfigurable wires by hardwired circuit-switched interconnects for the inter-IP communication. Specifically, we present hardwired crossbars and a circuit-switched NoC interconnect fabric. We describe the advantages of the hardwired networks evidenced by the quantified performance analysis, network simulation, and an implementation. As a result, the hardwired networks provide two orders of magnitude better performance per area than the networks that are mapped onto the reconfigurable fabric.