This letter presents an ultrawideband (UWB) radar for occupancy and vital signs detection. The proposed burst-chirp operation achieves > 30 imes power reduction and abundant margin for the UWB spectrum regulations. With the proposed Domino chirp generation and time-domain predistortion, the radar has a fast chirp slope of 0.7 GHz/40 μ ext{s} and a low RMS error of 0.5 MHz. Fabricated in a 40-nm CMOS process, the presented radar consumes a record-low power of 680 μ ext{W} and can detect human respiration and heartbeat up to 15 and 5 m, respectively.@en

For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution <20 cm. However, their power consumption is typically in the order of 100's of mW, preventing long-term maintenance-free battery-powered operations. Although mains power can be used to supply such radars, this is not always available, depending on the location and the building type, and the installation cost (e.g., power routing) is significantly higher than for battery-powered ones. In this work, a burst-chirp radar with an energy-efficient chirp generation is proposed, leading to a record-low power consumption of 680 μW.

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This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.@en