In this contribution we present the developments and current performance of calibration substrates manufactured on 150 mm Quartz wafers (675 μm thick) based on a CMOS process technology. The passive structures required to realize on-wafer vector network analyzer calibration standards are benchmarked against commercially available (i.e., Alumina) substrates. First, an analysis of the process stability is presented for both reflective and resistive impedances across the entire wafer (i.e., 24 dies). Full-wave EM simulations are employed to realize accurate calibration artefact models aiming to achieve state-of-the-art calibration accuracy. The calibration quality in finally benchmarked on an independent line realized in the back-end-of-line of a Silicon based technology up to 67.5 GHz.@en

In this contribution we present the developments and current performance of calibration substrates manufactured on 150 mm Quartz wafers (675 μm thick) based on a CMOS process technology. The passive structures required to realize on-wafer vector network analyzer calibration standards are benchmarked against commercially available (i.e., Alumina) substrates. First, an analysis of the process stability is presented for both reflective and resistive impedances across the entire wafer (i.e., 24 dies). Full-wave EM simulations are employed to realize accurate calibration artefact models aiming to achieve state-of-the-art calibration accuracy. The calibration quality in finally benchmarked on an independent line realized in the back-end-of-line of a Silicon based technology up to 67.5 GHz.@en

In this contribution we present the developments and current performance of calibration substrates manufactured on 150 mm Quartz wafers (675 μm thick) based on a CMOS process technology. The passive structures required to realize on-wafer vector network analyzer calibration standards are benchmarked against commercially available (i.e., Alumina) substrates. First, an analysis of the process stability is presented for both reflective and resistive impedances across the entire wafer (i.e., 24 dies). Full-wave EM simulations are employed to realize accurate calibration artefact models aiming to achieve state-of-the-art calibration accuracy. The calibration quality in finally benchmarked on an independent line realized in the back-end-of-line of a Silicon based technology up to 67.5 GHz.@en

Nano-satellite IoT/M2M missions are gaining popularity in recent time. Various companies have launched their pilot missions last year in 2018 and all these companies intend to place a constellation in (V)LEO that can communicate with low power sensors on the ground (sometimes remote locations) and relay it back to the end-user who is monitoring these sensors. This paper discusses two possible architectures of using nano-satellites for low latency IoT/M2M, by presenting information such as, number of satellites needed, number of orbital planes needed and communication strategy. The first proposed architecture will comprise of a self-sustaining network of nano-satellites that communicate with low power, low data-rate sensors on the ground and relay the data to rest of the nano-satellites in the network using inter-satellite links, which is downlinked by a nano-satellite that is in the view of a ground station that is connected to IMT. The second proposed architecture will use nano-satellites to communicate with low power, low data-rate sensors on the ground and relay it to satellites that intend to provide internet from space (Mega-constellation). The internet constellations considered in this study for the second architecture are: Telesat’s constellation, SpaceX’s Starlink, OneWeb’s constellation, Astrome’s SpaceNet constellation and Audacy’s constellation. Using both these architectures, it can be seen that the latency can be reduced considerably. @en