We report on the characterization of single-photon avalanche diodes (SPADs) fabricated in standard 140-nm silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. As a methodology for SPAD optimization, a test structure array, called SPAD farm, was realized with several junctions, guard-ring structures, dimensions, etc. In this paper, characterization results of the most promising SOI CMOS SPAD are compared with state-of-the-art results reported in the literature.