High speed imagers find applications in many fields such as scientific and medical imaging, automotive applications, machine vision and much more. In this thesis, the design of a high speed, high dynamic range (HDR) CMOS sensor with electronic global shutter (GS) and flexible exposure control is presented. The sensor is designed in the 0.11μm CIS process, features 1k(H) x 1k(V) pixels and achieves frame rates greater that 10.000 fps.A review of the architecture of the sensor is given, along with functional illustrations for each comprising block. The quadrant-based approach is described, along with the selectable region-of-interest capability. The pixel design is a eleven-transistor (11T) pinned photodiode global shutter pixel, implementing HDR by means of two in-pixel capacitors. The design of the pipelined Sample & Hold, column gain and column-level Correlated Double Sampling (CDS) circuits are shown.

Imaging sensors are remarkable devices which are able to capture moments and present them in a form available to us for years to come. With the use of material properties and photon particles, charges can be produced which, in combination with electric circuitry, transform into information understandable to the human eye and eventually the brain. When a photon particle hits a silicon photodiode, an electron-hole pair forms. By using readout techniques optimized for noise, area and power, images of different quality can be read out. Imaging concepts such as Signal-to-Noise Ratio, Dynamic Range, Resolution, Contrast and more can be used to describe the quality of the sensor. These concepts of quality are of interest when designing an imaging sensor. Throughout this thesis, design methodologies are applied to both the field of Optical Tomography and Neural Networks.

Optical Tomography is an imaging technique capable of detecting the internal structure of a subject with the use of image sensors. Various Optical Tomography techniques exist such as Diffusion Optical Tomography, Optical Projection Tomography and Optical Coherence Tomography (OCT). Optical Coherence Tomography is of special interest due to published papers which show the potential of the use with CMOS image sensors. The technique is based on the Michelson interferometer which is used in order to retrieve data of micrometer resolution. A feasibility study was conducted on OCT which shows potential for future research due to its recent development using CMOS image sensors. A review of state-of-the-art solutions is presented. With the most recent publication on a CMOS image sensor in OCT, with a dynamic range of 66 dB and a frame rate of 730 frames per second, showed the possibility of retrieving OCT images of higher quality compared to conventional sensors.

Artificial Neural Networks are inspired by the complex structure of our brain. By using its unique way of parallel computation, algorithms are capable of teaching our electronic devices human capabilities such as speech and face recognition. Artificial Neural Networks are identified by neurons and synapses in analogy to the nervous system. In this thesis, pixel design concepts are applied to neural networks where the pixel structure is modelled as a neuron. As a part of a larger project, low power design cells are collected into a combined library and presented. The library, in the end of development, will be used for finalizing and optimizing the complete neural network. One of the project’s challenges was to design a novel absolute value filter. The filter’s importance is presented as a part of a learning algorithm where it takes an absolute value of the difference between two signals. The resulting filter is operational and has the low power dissipation of 87 nW. The area was minimized and includes 10 transistors and a current mirror. The signal gain is around -13.2 dB which shows attenuation of the signal. The amount of gain required for this structure, as part of the learning algorithm, is not yet determined. Future work includes improving the circuit’s gain with a gain boost technique and minimizing noise levels with the use of larger transistors and new technologies.