Voltage references are one of the fundamental building blocks for designing any analog processing circuit. It serves as a reference for Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), power/voltage regulators and other measurement and control circuits. The performance of all these circuits cannot be better than the performance of the reference. Hence, it is very important that the voltage reference is very robust and performs reliably under process, supply, temperature or noise variations (PVT & N). Today, with the development of scalable quantum computing, there is a need for such a reference operating at cryogenic temperatures. Currently, the state of the art quantum circuits operates at ∼20 mK. To process and control the information flow, to and from these quantum processors, one requires an analog circuit to operate as close as possible to the quantum circuit, so as to make the full system scalable and more reliable since no line interconnect to room-temperature electronics would be required. As a step towards that idea, it is desired to push the operating temperature of the classical circuits as low as 4 K where enough cooling power is available without disturbing the operation of the quantum circuit. One of the basic blocks to be shifted to cryogenic temperatures is the voltage reference circuit. This thesis presents a systematic design of such a cryogenic voltage reference block, taking into account the device and circuit performance at 4 K. The targeted specifications are comparable to the references designed for standard industrial temperature range (233 K to 400 K). However, it is designed to work over an extremely wide temperature range (4 K to 400 K) to understand how far one can stretch the circuits designed with conventional CMOS. Two different variants of references are presented with the simulated performance of both over the industrial temperature range. A novel approach towards higher-order compensation is also presented which is expected to perform better than conventional CMOS reference over a wide range. To test their performance over the entire operating range (4 K to 400 K) and verify the designs, a tape-out is planned for October 2019.