As recon?gurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS tools use the original source code and transforms this to a hardware description. The quality of the original source code is of great in?uence for the resulting hardware. In many data intensive applications, memory accesses form a bottleneck. To improve the performance of the hardware implementation, the execution behavoir of these accesses must ?rst be optimized in the software source code. While doing this, an analyzer providing crucial information about the algorithm itself helps reduce engineering time. This thesis work presents a framework which is capable of providing information about memory accesses and operations executed within an algorithm. The reports containing this information can be generated on a per function or per loop basis. This enables the engineer to ?nd loop speci?c information, which can be used to optimize the algorithm and to provide crucial pipeline information to the HLS tool. An Optical Flow algorithm is used as case study to demonstrate the functionality of the framework. A massive speedup of a factor of 13.7 was achieved while the area increased only with a factor of 1.47. This demonstrates the e?ectiveness of the presented framework.

As recon?gurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS tools use the original source code and transforms this to a hardware description. The quality of the original source code is of great in?uence for the resulting hardware. In many data intensive applications, memory accesses form a bottleneck. To improve the performance of the hardware implementation, the execution behavoir of these accesses must ?rst be optimized in the software source code. While doing this, an analyzer providing crucial information about the algorithm itself helps reduce engineering time. This thesis work presents a framework which is capable of providing information about memory accesses and operations executed within an algorithm. The reports containing this information can be generated on a per function or per loop basis. This enables the engineer to ?nd loop speci?c information, which can be used to optimize the algorithm and to provide crucial pipeline information to the HLS tool. An Optical Flow algorithm is used as case study to demonstrate the functionality of the framework. A massive speedup of a factor of 13.7 was achieved while the area increased only with a factor of 1.47. This demonstrates the e?ectiveness of the presented framework.

As recon?gurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS tools use the original source code and transforms this to a hardware description. The quality of the original source code is of great in?uence for the resulting hardware. In many data intensive applications, memory accesses form a bottleneck. To improve the performance of the hardware implementation, the execution behavoir of these accesses must ?rst be optimized in the software source code. While doing this, an analyzer providing crucial information about the algorithm itself helps reduce engineering time. This thesis work presents a framework which is capable of providing information about memory accesses and operations executed within an algorithm. The reports containing this information can be generated on a per function or per loop basis. This enables the engineer to ?nd loop speci?c information, which can be used to optimize the algorithm and to provide crucial pipeline information to the HLS tool. An Optical Flow algorithm is used as case study to demonstrate the functionality of the framework. A massive speedup of a factor of 13.7 was achieved while the area increased only with a factor of 1.47. This demonstrates the e?ectiveness of the presented framework.

As recon?gurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS tools use the original source code and transforms this to a hardware description. The quality of the original source code is of great in?uence for the resulting hardware. In many data intensive applications, memory accesses form a bottleneck. To improve the performance of the hardware implementation, the execution behavoir of these accesses must ?rst be optimized in the software source code. While doing this, an analyzer providing crucial information about the algorithm itself helps reduce engineering time. This thesis work presents a framework which is capable of providing information about memory accesses and operations executed within an algorithm. The reports containing this information can be generated on a per function or per loop basis. This enables the engineer to ?nd loop speci?c information, which can be used to optimize the algorithm and to provide crucial pipeline information to the HLS tool. An Optical Flow algorithm is used as case study to demonstrate the functionality of the framework. A massive speedup of a factor of 13.7 was achieved while the area increased only with a factor of 1.47. This demonstrates the e?ectiveness of the presented framework.