Over the past decades, ultrasound imaging has made considerable progress based on the advancement of imaging systems as well as transducer technology. With the need for advanced transducer arrays with complex designs and technical requirements, there is also a need for suitable tools to characterize such transducers. However, despite the importance of acoustic characterization to assess the performance of novel transducer arrays, the characterization process of highly complex transducers might involve various manual steps, which are laborious, time-consuming, and subject to errors. These factors can hinder the full characterization of a prototype transducer, leading to an under-representation or inadequate evaluation. To come to an extensive, high-quality evaluation of a prototype transducer, the acoustic characterization of each transducer element is indispensable in both transmit and receive operations. In this paper, we propose a pipeline to automatically perform the acoustic characterization of a matrix transducer using a research imaging system. The performance of the pipeline is tested on a prototype matrix transducer consisting of 960 elements. The results show that the proposed pipeline is capable of performing the complete acoustic characterization of a high-element count transducer in a fast and convenient way.

High frame rate three-dimensional (3D) ultrasound imaging would offer excellent possibilities for the accurate assessment of carotid artery diseases. This calls for a matrix transducer with a large aperture and a vast number of elements. Such a matrix transducer should be interfaced with an application-specific integrated circuit (ASIC) for channel reduction. However, the fabrication of such a transducer integrated with one very large ASIC is very challenging and expensive. In this study, we develop a prototype matrix transducer mounted on top of multiple identical ASICs in a tiled configuration. The matrix was designed to have 7680 piezoelectric elements with a pitch of 300 μm × 150 μm integrated with an array of 8 × 1 tiled ASICs. The performance of the prototype is characterized by a series of measurements. The transducer exhibits a uniform behavior with the majority of the elements working within the −6 dB sensitivity range. In transmit, the individual elements show a center frequency of 7.5 MHz, a −6 dB bandwidth of 45%, and a transmit efficiency of 30 Pa/V at 200 mm. In receive, the dynamic range is 81 dB, and the minimum detectable pressure is 60 Pa per element. To demonstrate the imaging capabilities, we acquired 3D images using a commercial wire phantom.

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of -109.1 dB and can deliver a maximum of 14 W into an 8- \Omega load with 93% efficiency while occupying a silicon area of 5 mm2.