The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10⁵ cm² V⁻¹ s⁻¹ and low percolation density of 6.9(1) × 10¹⁰ cm⁻². These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

We grow strained Ge/SiGe heterostructures by reduced-pressure chemical vapor deposition on 100 mm Ge wafers. The use of Ge wafers as substrates for epitaxy enables high-quality Ge-rich SiGe strain-relaxed buffers with a threading dislocation density of ( 6 ± 1 ) × 10 5 cm − 2 , nearly an order of magnitude improvement compared to control strain-relaxed buffers on Si wafers. The associated reduction in short-range scattering allows for a drastic improvement of the disorder properties of the two-dimensional hole gas, measured in several Ge/SiGe heterostructure field-effect transistors. We measure an average low percolation density of ( 1.22 ± 0.03 ) × 10 10 cm − 2 and an average maximum mobility of ( 3.4 ± 0.1 ) × 10 6 cm 2 / Vs and quantum mobility of ( 8.4 ± 0.5 ) × 10 4 cm 2 / Vs when the hole density in the quantum well is saturated to ( 1.65 ± 0.02 ) × 10 11 cm − 2 . We anticipate immediate application of these heterostructures for next-generation, higher-performance Ge spin-qubits, and their integration into larger quantum processors.

As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

We grow 28Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, 28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8 ± 0.5) × 10 5 cm2/V s and a low mean percolation density of (9 ± 1) × 10 10 cm-2. From the analysis of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1 ± 0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5 ± 0.6) × 10 4 cm2/V s and (40 ± 3) μ eV, respectively, and a small mean Dingle ratio of (2.3 ± 0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.