Photovoltaic (PV) modules have considerable difficulty when exposed to shading since even partial blockages can significantly reduce energy production. To make the PV module shade-resilience, sub-module maximum power point tracking(MPPT) can be done for each string in the module. One way of doing it is by using converters at the sub-module level, which can track the string's maximum power point(MPP) by varying its duty cycle. In conventional converter design, inductors are the bulkiest and costliest component used, which eventually makes the application of sub-module MPPT less cost-effective. However, a literature study found that solar cell generates self-impedance under biasing, which opens up the idea for cell-level integration of power electronics. This thesis aims to validate the possibility of using the self-inductance generated in the solar cell for partially designing the DC/DC converter on the solar cell such that MPPT can be performed at the sub-module level. To accomplish this objective, two distinct strategies have been examined: The utilization of solar cell self-inductance for designing a conventional boost converter on a solar cell surface and the integration of a planar coil onto a solar cell for partially designing a DC/DC boost converter.

Several promising photovoltaic (PV) concepts are supported by transistors. Along with the growth of PV capacity in the urban environment, issues related to partial shading highlight the interest in more shade-tolerant PV systems. An example of technologies improving a PV module’s energy yield under partial shading is the submodule power optimizer, including a power converter that operates sub-module maximum power point tracking (MPPT). Alternately, reconfigurable PV modules enable dynamic reconfiguration of the solar cells’ interconnections to optimize the energy yield depending on the irradiance distribution. Both technologies make use of transistors as fundamental components. Integrating the latter into the solar cell wafer might be a solution for cost reduction and reliability improvement and thus support such concepts. Moreover, that kind of transistor integration can have applications in solar cell-embedded electronic and digital devices.

In this thesis, a lateral metal-oxide-semiconductor field-effect transistor (MOSFET) and an interdigitated back-contacted (IBC) solar cell are integrated into the same crystalline silicon (c-Si) wafer. A combined process flow is developed to manufacture both components with a minimum number of additional steps compared to single-component manufacturing processes. One criterion for this is a high similarity in the design of the device. Therefore, a tunneling oxide passivated contact (TOPCon) solar cell structure is used, involving polycrystalline silicon (poly-Si) at the device’s backside. Similarly, the MOSFET’s gate is made of a highly doped poy-Si film. Ion implantation is used as a common doping process.

Both solar cells and transistors that were manufactured with the combined process flow are first characterized separately. The highest efficiencies obtained for n-type and p-type solar cells are 20.29% and 20.66%, respectively. This is achieved thanks to multiple combined passivation approaches including TOPCon, wet poly-Si etching, a front-side hydrogenated amorphous silicon (a-Si:H) film, and hydrogenated silicon nitride on both sides of the device. Different MOSFET layouts are explored to make the device able to handle relatively large currents. It is found that introducing several drain-source pairs in parallel is more efficient than increasing the channel width to reduce the on-resistance. The on-resistance is further minimized with a gate length reduction and wet chemical poly-Si etching. As expected, the comparison of PMOS and NMOS (MOSFETs built on n-type and p-type wafers, respectively) shows better on-performance for the latter. A minimum on-resistance value of 1 Ω is then obtained. However, a higher leakage current consistently seems to come along with reduced on-resistance; i.e., higher on-performance is coupled with lower off-performance. Finally, experiments are performed combining both components. Under illumination, the MOSFET exhibits lower off-performance due to the photovoltaic effect. However, this effect does not affect the on-performance of the component. The monolithically connected components exhibit I-V characteristics that depend on the applied MOSFET’s gate potential. In the on-mode, the solar cell maintains more than 95% of the conversion efficiency compared to the efficiency measured with the same solar cell without the transistor. However, a non-zero current is obtained in the off-mode, exhibiting low transistor blocking capability. Nevertheless, the large difference in characteristics obtained between the on- and off-modes proves the feasibility of integrating a solar cell and a transistor on the same substrate with a minimum number of additional processing
steps.

As PV capacity in urban areas keeps increasing, non-uniform illumination of panels will become more prevalent. This could cause the partial shading to become more frequent, reducing PV system performance. Some ways to solve this problem is by the use of module-level maximum power point tracking (MPPT), micro inverters, or reconfigurable modules. To this end, the integration of metal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells could play an important role in future methods to prevent this issue. This integration of a MOSFET allows for module level, and potentially sub-module level, MPPT, as well as the application of reconfigurable modules to circumvent this issue. This thesis aims to optimize the MOSFET dimensions and fabrication process to be able to handle the short circuit current and open circuit voltage of a PV module, and to analyze the optoelectrical effects under direct illumination of the MOSFET performance. In this thesis report, a flowchart is proposed on how to fabricate a working power MOSFET while combining the fabrication techniques used in the Integrated Circuits and Photovoltaics industries. This process closely resembles the fabrication of solar cells and uses similar techniques used to fabricate interdigitated back contacted (IBC) solar cells. It is shown that It is shown that the use of wider devices can reduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a device with a width of 5000𝜇m. For NMOS devices a similar relationship can be seen where the channel resistance is 49Ω for a width of 500𝜇m and 8.1Ω for a device width of 5000𝜇m. The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOS device with a width of 500𝜇m to less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOS this density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on the effects of implantation energy and scattering layer thicknesses showed that both lower energies and thicker layers yield higher drain currents and lower channel resistance. A possible explanation for this is that a shift in the threshold voltage increased the overdrive voltage and therefore the drain current. In the investigation of the effects of direct illumination on the electrical characteristics of the device it was found that the threshold voltage increases for PMOS devices from -0.21V under no illumination to -0.06V under full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOS devices from 0.06V under no illumination to -0.15V under full spectrum illumination at 1000𝑊/𝑚2. Furthermore the off state gate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and by a factor of 107 for PMOS devices. The electron mobility of the NMOS transistor increases with incident light, improving the drain current gate voltage relationship. The channel resistance for the NMOS devices improved between 5-13%, depending on the intensity of the illumination, while the channel resistance of the PMOS increases up to 2%.A similar effect for the hole mobility of the PMOS was not observed. Similarly, the channel resistance of the NMOS transistor improved, possibly due to the shift in threshold voltage or improved electron mobility. This improvement in performance was not recognized for PMOS transistors, however. A flowchart has been proposed for a process in which a MOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC) solar cell while combining as many steps as possible from their respective flowcharts to reduce complexity and costs, possibly leading the best balance between MOSFET and IBC fabrication.As PV capacity in urban areas keeps increasing, non-uniform illumination of panels will become more prevalent. This could cause the partial shading to become more frequent, reducing PV system performance. Some ways to solve this problem is by the use of module-level maximum power point tracking (MPPT), micro inverters, or reconfigurable modules. To this end, the integration of metal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells could play an important role in future methods to prevent this issue. This integration of a MOSFET allows for module level, and potentially sub-module level, MPPT, as well as the application of reconfigurable modules to circumvent this issue. This thesis aims to optimize the MOSFET dimensions and fabrication process to be able to handle the short circuit current and open circuit voltage of a PV module, and to analyze the optoelectrical effects under direct illumination of the MOSFET performance. In this thesis report, a flowchart is proposed on how to fabricate a working power MOSFET while combining the fabrication techniques used in the Integrated Circuits and Photovoltaics industries. This process closely resembles the fabrication of solar cells and uses similar techniques used to fabricate interdigitated back contacted (IBC) solar cells. It is shown that It is shown that the use of wider devices can reduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a device with a width of 5000𝜇m. For NMOS devices a similar relationship can be seen where the channel resistance is 49Ω for a width of 500𝜇m and 8.1Ω for a device width of 5000𝜇m. The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOS device with a width of 500𝜇m to less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOS this density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on the effects of implantation energy and scattering layer thicknesses showed that both lower energies and thicker layers yield higher drain currents and lower channel resistance. A possible explanation for this is that a shift in the threshold voltage increased the overdrive voltage and therefore the drain current. In the investigation of the effects of direct illumination on the electrical characteristics of the device it was found that the threshold voltage increases for PMOS devices from -0.21V under no illumination to -0.06V under full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOS devices from 0.06V under no illumination to -0.15V under full spectrum illumination at 1000𝑊/𝑚2. Furthermore the off state gate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and by a factor of 107 for PMOS devices. The electron mobility of the NMOS transistor increases with incident light, improving the drain current gate voltage relationship. The channel resistance for the NMOS devices improved between 5-13%, depending on the intensity of the illumination, while the channel resistance of the PMOS increases up to 2%.A similar effect for the hole mobility of the PMOS was not observed. Similarly, the channel resistance of the NMOS transistor improved, possibly due to the shift in threshold voltage or improved electron mobility. This improvement in performance was not recognized for PMOS transistors, however. A flowchart has been proposed for a process in which a MOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC) solar cell while combining as many steps as possible from their respective flowcharts to reduce complexity and costs, possibly leading the best balance between MOSFET and IBC fabrication. As PV capacity in urban areaskeeps increasing, non-uniform illumination of panels will become more prevalent.This could cause the partial shading to become more frequent, reducing PVsystem performance. Some ways to solve this problem is by the use ofmodule-level maximum power point tracking (MPPT), micro inverters, orreconfigurable modules. To this end, the integration ofmetal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells couldplay an important role in future methods to prevent this issue. Thisintegration of a MOSFET allows for module level, and potentially sub-modulelevel, MPPT, as well as the application of reconfigurable modules to circumventthis issue. This thesis aims to optimize the MOSFET dimensions and fabricationprocess to be able to handle the short circuit current and open circuit voltageof a PV module, and to analyze the optoelectrical effects under directillumination of the MOSFET performance. In this thesis report, a flowchart isproposed on how to fabricate a working power MOSFET while combining thefabrication techniques used in the Integrated Circuits and Photovoltaicsindustries. This process closely resembles the fabrication of solar cells anduses similar techniques used to fabricate interdigitated back contacted (IBC)solar cells. It is shown that It is shown that the use of wider devices canreduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a devicewith a width of 5000𝜇m.For NMOS devices a similar relationship can be seen where the channelresistance is 49Ω for a width of 500𝜇mand 8.1Ω for a device width of 5000𝜇m.The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOSdevice with a width of 500𝜇mto less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOSthis density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on theeffects of implantation energy and scattering layer thicknesses showed thatboth lower energies and thicker layers yield higher drain currents and lowerchannel resistance. A possible explanation for this is that a shift in thethreshold voltage increased the overdrive voltage and therefore the draincurrent. In the investigation of the effects of direct illumination on theelectrical characteristics of the device it was found that the thresholdvoltage increases for PMOS devices from -0.21V under no illumination to -0.06Vunder full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOSdevices from 0.06V under no illumination to -0.15V under full spectrumillumination at 1000𝑊/𝑚2. Furthermore the off stategate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and bya factor of 107 for PMOS devices. The electron mobility of the NMOS transistorincreases with incident light, improving the drain current gate voltagerelationship. The channel resistance for the NMOS devices improved between5-13%, depending on the intensity of the illumination, while the channelresistance of the PMOS increases up to 2%.A similar effect for the hole mobilityof the PMOS was not observed. Similarly, the channel resistance of the NMOStransistor improved, possibly due to the shift in threshold voltage or improvedelectron mobility. This improvement in performance was not recognized for PMOStransistors, however. A flowchart has been proposed for a process in which aMOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC)solar cell while combining as many steps as possible from their respectiveflowcharts to reduce complexity and costs, possibly leading the best balancebetween MOSFET and IBC fabrication.    

With the integration of solar panels in urban areas, where shading is a common issue, it is desired to realize more shade-resilient designs. A DC-DC boost converter is an electronic device that can be used for maximum power point tracking (MPPT). When implementing MPPT at sub-module level, the shade resilience of the module can be increased. This thesis aims to investigate the feasibility of implementing planar inductors into c-Si solar cells using the numerical simulation software COMSOL Multiphysics®. Through simulations, the inductance and resistance values for various planar coil geometries were obtained. Subsequently, the feasibility of using these coils in a sub-module DC-DC boost converter was investigated. For this study, a specific case was assumed where a Gen 2 Cell - 160 mm c-Si cell is used with a DC-DC boost converter with a duty cycle of 0.5 and a current ripple of 20%. Given the parameters from these devices, the minimum required inductance of 1.20 μH for a frequency of 200 kHz and 2.40 μH for a frequency of 100 kHz were obtained. The series resistances that can be added to the solar cell while still maintaining high efficiency, range from 1.0 mΩ to 4.8 mΩ, for a 1% to a 5% power loss, respectively. This is all for single-cell power conversion. Two different approaches have been examined; the screen-printed coil(s) approach and the screen printing thickness exceeding coil(s) approach. The former studies coils that do not exceed the maximum thickness achievable with screen printing. As such, these coils could be simpler to implement into a solar cell production line than coils with a higher thickness. In this research, for thicknesses below 300 μm a best-case scenario is studied where the skin effect is neglected. The latter studies a larger range of thicknesses, not taking any specific production method into account, but the skin and proximity effect is taken into account. The screen-printed approach is limited to a thickness range of 10 μm to 200 μm, thus simulated by the 2D model. For the air-core single-cell inductors for DC-DC boost converter applications, the inductance and resistance values were either below the 1.20 μH threshold or above the 4.8 mΩ threshold, respectively. These thresholds change depending on the number of series-connected cells. The inductance of a planar inductor can be boosted up to 200% when adding a magnetic material in a sandwich structure, however, this will also increase the costs of the application. In a boosted-inductance case, the 3-turn coil with a thickness of 200 μm, and a 5% power loss is the only configuration that is feasible for a 200 kHz DC-DC boost converter application, with an inductance of 1.569 μH and a resistance of 3.45 mΩ. By increasing the number of coils per cell, the power dissipation in the coils can be reduced. Using this approach, six feasible topologies can be created. One of those is the nine parallel-connected 8-turn coils with a thickness of 200 μm, reaching an inductance of 1.210 μH and a resistance of 3.186 mΩ, allowing for a 200 kHz DC-DC boost converter application without any magnetic inductance increase. All six options are feasible for integration on a single cell using screen printing, however, the actual resistances will be higher due to the skin and proximity effect, and single-cell integration will be too expensive for industrial applications. When studying thicknesses above the screen printing limit, only the 4-turn coil with a thickness of 300 μm, a magnetically increased inductance of 2.718 μH, and a resistance of 4.01 mΩ, is feasible for the 100 and 200 kHz frequencies. This case however does neglect the skin effect. For the 3D model and thicknesses above 400 μm, the skin effect significantly impacts the resistance. When series connecting multiple cells to a single coil, the only feasible option is the eight-cell connected 8-turn coil for a thickness of 200 μm and 300 μm, both reaching a magnetically increased inductance of 10.431 μH and resistance of 23.33 mΩ and 15.56 mΩ, respectively.