This thesis describes the design and implementation of a controller and GUI for an AI loudspeaker filter design program. This program uses a genetic algorithm to create a combination of analog passive filters, one for each driver in a loudspeaker system. In the controller, two cost functions are designed to evaluate these filter combinations, and when the genetic algorithm has created its final filters, unnecessary components are removed and all component values are optimized. A GUI is created to allow easy user interaction.
For selecting a cost function, not enough data was obtained to make a deliberate decision based on performance. Therefore, this decision was based on theory and subordinate features. Nonetheless, the final program is able to create flat acoustic responses in a margin of 2 dB.

Machine learning can be effectively applied in control loops to robustly make optimal control decisions. There is increasing interest in using spiking neural networks (SNNs) as the apparatus for machine learning in control engineering, because SNNs can potentially offer high energy efficiency and new SNN-enabling neuromorphic hardwares are being rapidly developed. A defining character of control problems is that environmental reactions and delayed rewards must be considered. While reinforcement learning (RL) provides the fundamental mechanisms to address such problems, realizing these mechanisms in SNN learning has been underexplored. Previously, schemes of spike timing dependent plasticity (STDP) learning modulated by factors of temporal difference (TD-STDP) or reward (R-STDP) have been proposed for RL with SNN. Here we designed and implemented an SNN controller to explore and compare these two schemes by considering Cart-Pole balancing as a representative example. While the TD-based learning rules are very general ones, the resulted model exhibits rather slow convergence, producing noisy and imperfect results even after prolonged training. We show that by integrating the understanding of the dynamics of the environment into the reward function of R-STDP, a robust SNN-based controller can be learnt much more efficiently than by TD-STDP. The work of this master thesis project has also been published as a paper in Electronics, Vol. 12.

Spiking Neural Networks(SNN) have been widely leveraged by neuromorphic systems due to their ability to closely mimic biological neural behavior, where information is exchanged and received between neurons in the form of sparse events(spikes). Such neuromorphic systems are highly energy-efficient because the use of a global clock can be avoided by asynchronous event-driven operations. Neurons, as the basic processing units of neuromorphic systems, are required to be low-power and high-speed for the implementation of complex networks. In this work, two fully event-driven digital Integrate-and-Fire(IF) neuron design is presented. Both design exploits the hierarchical structure, which allows the synaptic weights can be accumulated by local compute units in parallel. Instead of using handshake protocols, the proposed design generates on-demand event pulses to drive the weight accumulation, so we call it self-timed. Both neurons are designed by SystemVerilog and synthesized in TSMC 28nm technology. According to the synthesis results, both designs can finish the accumulation of 1024 6-bit weights within 100ns, with a power consumption of 0.055pJ per spike and 0.23pJ per spike respectively.

Scalable universal quantum computers require classical control hardware, physically close to the quantum devices at cryogenic temperatures. Such classical controllers need digital memory for various applications, ranging from high-speed queues to high-speed and low-speed lookup tables and working memory. The power consumption of the memories should be within the available cooling power at these temperatures. To obtain the best memory design with the lowest power consumption, cryogenic-CMOS characteristics need to be taken into account during design. This thesis aims to develop a model that can be used to find the optimal memory cell design for each application, while taking area, latency, error rate, and power constraints into account. A model is developed to estimate the error rate and power consumption of a memory core for four cell designs, namely three embedded dynamic cell designs and one static cell design, over a range of applications in terms of memory operation frequency and read/write operation ratio. The model is constructed using room temperature and 233 K simulation data of individual cells and peripherals from a TSMC 40 nm technology. To estimate the error rate and power consumption at 4.2 K, the model is extended with empirical cryogenic-CMOS characteristics, such as an increase in threshold voltage and a steeper subthreshold slope, since good device models at this temperature are not available. To verify and improve the memory model, a test chip in TSMC 40 nm technology is designed, which includes eight fully-custom memories with two threshold-variations of each of the four cell designs to mitigate the cryogenic-CMOS threshold voltage increase. These memories are connected to an on-chip programmable microcontroller through a bus which enables flexible and high-speed testing without the need for high-speed I/O. This chip design is taped out and will be measured to verify and refine the model. At room temperature, the static cell design outperforms the dynamic cells in all memory applications with less than 10⁷ operations per second. However, at cryogenic temperatures, the embedded dynamic cell designs become feasible for applications with more than 300 operations per second, due to the significantly reduced refresh rate. The best embedded dynamic cell design depends on the read/write memory operation ratio required by the application. After verification and improvement of the memory model based on the measurement results from the test chip, this model can be used to find the best cell design for a given application based on its operation frequency and read/write operation ratio. Apart from comparing the performance of a single memory design at room temperature and 4.2 K, this work also allows for direct comparison between the different memory cells designs, designed with the same technology, architecture, peripherals, and by the same design rules. Since only a single architecture is used with a single design for each of the peripherals, further optimisation is required for a cryogenic-optimised full memory design.

LoRaWAN is a public Wireless Sensor network with excellent properties like being long-range, low-energy radios and resulting in long battery life. Devices are connected to this network through gateways, and they will run in that deployment for years without replacement. Therefore, bugs and security issues in such devices' firmware are present for a long time, unless firmware updates are applied to fix them. Firmware-Updates Over-The-Air (FUOTA) is a firmware update application framework for LoRaWAN, but packet loss is an unsolved issue for such firmware updating frameworks. State-of-the-art packet dissemination uses the Low-Density Parity Checks (LDPC), but this has decoding overhead. Also, it is inflexible due to its fixed-rate nature. The code can not be dynamically adjusted to adapt to temporary changes in channel conditions.
In this work, we provide critical analysis to justify replacing Low-Density Parity Checks code (LDPC) proposed in FUOTA with the famous code Random Linear Network Coding (RLNC). The benefit of RLNC shows when scaling to multicast networks using LoRaWAN FUOTA as fewer messages need to be exchanged to serve the complete network of firmware updates. An analysis is presented on how to configure the finite field size, generation size, and redundancy for generation-based RLNC. The parameters are optimized to cope with the worst-case packet-error rate. As such, RLNC can optimally counter every lost packet with redundancy with near-zero decoding overhead. Since devices sleep after decoding a set of fragments, or the generation, sending additional fragments does not decrease efficiency. Finally, the decoding probability is provided as an analytical tool to show that a specific amount of redundancy can deal with a specific worst-case packet-error rate.
To evaluate and test the RLNC code for LoRa, embedded firmware and terminal software have been developed to do indoor and outdoor measurements. This testbed has been developed with a custom control plane replacing all FUOTA MAC layer modules (Fragmentation, Multicast, Synchronization, Device Management, etc.). Therefore, it can be shaped into custom network configurations meant for evaluating the firmware updating process without having to set up infrastructures like ChirpStack or TheThingsStack. Our work's testbed can isolate the decoding process and evaluate it for artificial packet drops.
Results are presented, which show that systematic coding phase of LDPC will perform poorly compared to RLNC. This systematic phase is at least as large as the firmware update. Between 38% to 88% improvement in decoding success is found by using RLNC in case of varying network conditions due to burst loss.

Implantable Medical Devices (IMDs) are deployed in patients to treat a range of medical conditions. Technological advancements have enabled manufacturers to fit IMDs with specialized hardware that accelerates compute-intensive medical therapies next to a software-run host processor. However, mostly hardware acceleration is found in the form of ASIC peripherals next to a host processor in state-of-the-art IMDs, while low-power FPGAs could provide a comparable performance gain with the added benefit of the upgradability of functionality. Existing literature about low-power FPGAs focuses on new algorithms or performance improvements, while largely ignoring power and energy analysis, the latter being the most limiting factor in the IMD environment. This thesis investigates under what conditions FPGAs could be added to IMDs by developing two use cases: an FPGA securing wireless communication, and accelerating a neural network aiding medical therapies that depend on pattern detection. These cases are evaluated on FPGA, eFPGA and MCU with ASIC peripheral platforms, from which performance, energy usage and prospected IMD battery life is derived. On one end, it was found that AES encryption used 4.4 times the energy of an MCU hardware-accelerated implementation while being 17% slower. However, employing lightweight ciphers on the FPGA closes this gap. Furthermore, adding an FPGA results in only a 7.5% decrease in battery life when the FPGA is shut off during idling to combat its high static current draw. Running an FPGA-accelerated neural network is feasible if the active time is 6.5 minutes per day. With weekly recharging, continuous monitoring is possible. Using an eFPGA, which is an embedded FPGA fabric integrated within an MCU, results in using only 12% to 21% of the FPGA package area and is almost 2 times as energy efficient under 2 minutes daily usage as an FPGA. As FPGAs in IMDs is a novel field, research was done in legal regulation of IMDs, where it was found that existing regulations on software devices also applies to FPGAs. Therefore, all obstacles of the technical and legal kind have been removed that hold IMD manufacturers from using FPGAs in their devices.

Computation-In-Memory (CIM) employing Resistive-RAM
(RRAM)-based crossbar arrays is a promising solution to implement Neural Networks (NNs) on hardware, such that they are efficient with respect to consumption of energy, memory, computational resources, and computation time. In this respect, Binary NNs (BNNs), where the weights obtain single binary values, are inherently suitable for cost-effective CIM-based NN implementations. However, RRAM devices, due to variability and reliability issues, restrict the applicability of CIM-based NN. To address this issue and towards a low-cost NN hardware realization, in this thesis, we: a) thoroughly investigate the impact of RRAM faults on the inference accuracy of RRAM-based BNNs, and b) propose three complementary fault-tolerance techniques to mitigate the impact of RRAM faults on the BNN's accuracy. These techniques are namely: a) a fault-tolerant activation function, b) a redundancy and weight range adjustment scheme and c) a retraining technique. Evaluation results compiled on the MNIST, Fashion-MNIST, and CIFAR-10 datasets demonstrate that the proposed techniques can improve the inference accuracy in the presence of RRAM faults by up to 20%, 40%, and 80%, respectively. Moreover, comparisons with certain related state-of-the-art fault-tolerance frameworks indicate that the proposed techniques yield competitive results.

Radar systems have been used for decades to detect targets on the ground and in the air. The radar signal is transformed into a range-doppler image that distinguishes each detected object by range and velocity for further processing. A target detection algorithm is used to filter noise and clutter. Each target can be in a region with a different noise level; a simple threshold would yield false positives or miss detections depending on this value. To solve this problem, a Constant False Alarm Rate or CFAR is desirable. A CFAR detector estimates the noise surrounding each target and uses a dynamic threshold based on this.

Spiking Neural Networks are the third generation of Artificial Neural Networks where, instead of continuous signals, the input is encoded into trains of spikes over time. These networks have a potentially efficient hardware implementation instead of the older generation Artificial Neural Networks and could run directly at the sensor edge, lowering latency and power consumption.

This thesis will explore a Spiking Cell Averaging CFAR implementation and attempt to use its desirable properties like a temporal average over multiple radar frames, mimicking the non-coherent integration sometimes done in radar processing. It is shown that some configurations will behave similarly in a simulated environment with additive white gaussian noise.