The rapid growth of deep learning models, particularly Transformers, has far outpaced hardware scaling, increasing pressure on memory and compute efficiency. While INT8 quantization reduces memory requirements, it often sacrifices accuracy. Microscaling (MX) formats, such as MXINT8, address this trade-off by grouping INT8 values with a shared exponent, achieving FP32-level accuracy with up to 4 times memory savings. However, efficient execution of mixed integer–floating-point operations requires specialized hardware. Prior MX accelerators based on systolic arrays are limited by underutilized processing elements or the overhead of FP32 peripheries.

This work presents MXITA, a multi-dimensional systolic array accelerator for MX matrix multiplications in neural network workloads. The architecture introduces parameterization over (M, N, P, Q), enabling trade-offs between supported MX block sizes and FP32 peripheral reuse while sustaining high throughput. MXITA was designed, implemented, and integrated into the Snitch cluster, with verification ensuring functional correctness at both module and system levels.

Synthesis in GF22 technology demonstrates that MXITA achieves higher area efficiency than prior state-of-the-art MX accelerators by amortizing FP32 hardware across compute tiles and reducing periphery overhead. These results highlight the potential of multidimensional systolic arrays as scalable and efficient hardware for MX quantized deep learning workloads.

To achieve technical compliance with the Specific Operations Risk Assessment (SORA) framework is a significant challenge for Beyond Visual Line of Sight (BVLOS) drone operations. A reliable Command, Control, and Communication (C3) Data Link that meets SORA regulations is crucial for integrating drones safely in sectors that face high risk and labour shortages, such as inspection of long power transmission lines and wind turbines. In this work, we focus on C2 design aspects of an in-house data link tailored to BVLOS drone operations. Central to our design approach is the operational and mission capability diagram, which bridges the practical operational needs with key SORA objectives.

We implement a systematic process to translate relevant SORA objectives into quantifiable technical requirements, referencing 3GPP standards and JARUS guidelines. Subsequently, we design a sequence diagram mapping C2 data link functions to operational scenarios, which transforms into a logical architecture supporting modular Models-Based Systems Engineering (MBSE).

We perform test and results show data received by the Ground Control Station (GCS) server increased by threefold while latency reduced by 92\% by making improvements to the Scheduler and Link Manager modules respectively. In addition, we design a Link Manager simulation to offer clear metric visualisation to enable more confidence in operator assessment before physical flight trials. We show using simulations and experiments the benefits of our design. Our proposed framework enables wider drone deployment for BVLOS missions in the Netherlands and across Europe.

Fast and accurate readout of qubits is essential for feedback and error-correction protocols in scalable quantum processors. Current methods of readout in spin qubit processors require long times due to noise and drift present. The timing budget for feedback control and correction is further strained by the transfer of data to the host and back to the controller.
This thesis explores two complementary methods to speed up the readout: first, readout electronics integrated with programmable logic on the same boards reduce the latency of communication between the host and measurement setup, and second, a framework to reduce measurement times is devised by executing Machine Learning (ML) enhanced classification deployed on the same programmable logic.
We demonstrate the utility of the Radio-Frequency System on Chip (RFSoC) board for measurements of gate-defined semiconductor spin qubit devices. The design also incorporates an ML-accelerator for readout with a simulated latency of 58 ns for the classification of states.
This work enables the implementation of sophisticated readout techniques close to data acquisition electronics, which allows experiments that are not possible on conventional control electronics, which are either host-centric, requiring extensive calibration, or have block-box designs restricting hardware reprogrammability for specific experiments.

The human brain is arguably the most complex system we know of. For centuries, understanding the brain and the way it works has been of great concern to scientists. In 1952, the first mathematical model of a neuron was developed by Hodgkin and Huxley. This work pioneered the field of computational neuroscience, which studies the organization of the brain and the way it processes information. Modeling and simulation of neurons and small brain regions at the cellular level offer great insights into the details of brain mechanics, however, they are far away from clinical applications.

The Virtual Brain (TVB) is a simulation framework that takes a different approach to brain modeling. TVB reduces complexity at the micro level to achieve the macro level of brain modeling and simulation. This approach in brain modeling is referred to as Large-scale Brain Network or Neural-Mass Modeling. Additionally, TVB incorporates individual brain-imaging data with the models to achieve personalized, patient-specific digital brain twins. The digital brain twins can be used in clinical settings such as neurosurgeries and real-time brain-interface systems. However, building and utilizing such large-scale brain models requires high performance and low latency in terms of computation.

Today, heterogeneous architectures, due to their enhanced performance, energy efficiency, and better flexibility are being utilized increasingly in computing systems ranging from low-power edge devices to high-performance cloud infrastructures. Versal Adaptive Compute Acceleration Platform (ACAP) is a high-performance, heterogeneous computing platform developed by Xilinx/AMD. Versal ACAP offers an array of vector processors, specialized in artificial intelligence (AI) and signal processing workloads, next to the traditional programmable logic with extensive memory resources. The large-scale neural-mass simulation problem at hand has heterogeneous computational needs, which makes it interesting to see how it maps to the Versal ACAP. In this work, we explore the benefits and challenges of using heterogeneous systems (specifically, the Versal ACAP) in the high-performance workload of large-scale neural-mass simulation.

We designed and implemented a dataflow-style system for large-scale brain network simulation on the Versal ACAP. Two different versions of this system, namely AIE-Only and Heterogeneous, were developed in order to explore the capabilities of the Versal ACAP when accelerating our application. Compared to the current GPU version of TVB, the Heterogeneous implementation performed on average around 4× slower in terms of throughput. However, the Versal ACAP Heterogeneous implementation delivered around 13× lower latency, two orders of magnitude better energy efficiency, and around 2× better power efficiency compared to the GPU version of TVB. Although the Heterogeneous implementation falls short in terms of throughput compared to the GPU version, its lower latency and energy efficiency make it suitable for real-time applications that might use large-scale neural-mass modeling such as virtual surgery or brain interface devices.

This thesis discusses the digital signal processing involved in building a Vector Network Analyser for qubit readout. Existing VNAs are aggregated and used to construct a programme of requirements for this application. An architecture is constructed and explained, and the stages IQ decomposition and data reduction are analysed mathematically. The Discrete Fourier Transform is used to extract DC signals for this application and its properties are compared to different filters. Common digital logic functions such as AXI, Direct Digital Synthesis, and Direct Memory Access are explained, as well as the implementations of custom blocks for this application such as accumulators and a sequencer. These IP blocks are demonstrated individually and integrated to be implemented on a Red Pitaya STEMLab 125-14 board containing the Zynq 7010 SoC. The implementation is tested using simulated input signals and the resulting measurements are analysed. The implementation is found to have good absolute accuracy of within 2% of expected absolute amplitude, 1% of the expected relative amplitude and 8 mrad of expected relative phase. Modulation of the input signals is tested to work as expected and no major cross-modulation is found. Future improvements are identified and the limitations of the used data reduction are discussed in relation to a Vector Signal Analyser mode.

For microwave qubit readout in research applications, a Vector Network Analyser has been designed. The objective of this project was to design and build a modular, extensible VNA, containing open hard- ware and implemented in open-source software.
This thesis discusses the Python implementation of an interface between the digital signal processing step, taking place inside an FPGA, and the output of data to the user, being in graphical form and as systematical data structure to be stored on a PC. The interface is split up into a server, responsible for communicating with the FPGA on the same chip, and a client, which receives the measurement data from the server via the Transmission Control Protocol and controls the radio frequency signal genera- tors that serve as stimulus for the device under test and as local oscillator for downconversion.
An overview of VNAs and their application in this project is given in the first chapter. The programme of requirements and implementation overview are discussed next, followed by detailed explanations of the Python implementation of the server and client software. The achieved results satisfy the requirements for throughput, extensibility and data transfer overhead time. The thesis concludes with recommendations for future developments and extensions to this project.

Current backdoor attacks against federated learning (FL) strongly rely on universal triggers or semantic patterns, which can be easily detected and filtered by certain defense mechanisms such as norm clipping, comparing parameter divergences among local updates. In this work, we propose a new stealthy and robust backdoor attack with flexible triggers against FL defenses. To achieve this, we build a generative trigger function that can learn to manipulate the benign samples with an imperceptible flexible trigger pattern and simultaneously make the trigger pattern include the most significant hidden features of the attacker-chosen label. Moreover, our trigger generator can keep learning and adapt across different rounds, allowing it to adjust to changes in the global model. By filling the distinguishable difference (the mapping between the trigger pattern and target label), we make our attack naturally stealthy. Extensive experiments on real-world datasets verify the effectiveness and stealthiness of our attack compared to prior attacks on decentralized learning framework with eight well-studied defenses.

Quantum sensing technology has emerged as a promising field with superior sensitivity and accuracy in magnetic field sensing compared to conventional technologies. This breakthrough offers significant prospects in the biomedical sector, particularly in the realm of medical imaging.

This project focuses on the implementation of quantum sensing using an array of single Nitrogen Vacancy (NV) centers combined with an array of Single Photon Avalanche Diodes (SPADs). SPADs are available in various technologies and forms. To identify the optimal SPAD for this specific application, different SPADs with diverse parameters are designed on a chip using standard 40 nm TSMC process. These parameters include active area, active area shape and metal shielding.

The research aims to validate and characterize the performance of these distinct SPADs. However, during the validation tests, it was observed that the SPADs did not meet the criteria. The presence of ESD diodes on the chip introduced a low resistance current path, thereby hindering the characterisation process of the SPADs. Solutions to fix this problem and improve the system are provided.

The documented validation methods include general chip testing, establishing the I-V curves of the SPADs and avalanche and quenching testing. In addition, the characterisation methods for junction capacitance, dark count rate (DCR), photon detection probability (PDP) and time jitter are given.

For characterizing DCR and PDP a readout system is designed. It consists of an analog-to-digital converter (ADC), FPGA and Arduino. The data is communicated continuously to a PC. The ADC is not fully tested. On the other hand, the FPGA and Arduino are tested and verified to be sufficient for the DCR measurements. The readout system is too inaccurate for PDP measurements. A recommendation on how to make the readout system sufficient for PDP is given.

This thesis describes the design and implementation of a controller and GUI for an AI loudspeaker filter design program. This program uses a genetic algorithm to create a combination of analog passive filters, one for each driver in a loudspeaker system. In the controller, two cost functions are designed to evaluate these filter combinations, and when the genetic algorithm has created its final filters, unnecessary components are removed and all component values are optimized. A GUI is created to allow easy user interaction.
For selecting a cost function, not enough data was obtained to make a deliberate decision based on performance. Therefore, this decision was based on theory and subordinate features. Nonetheless, the final program is able to create flat acoustic responses in a margin of 2 dB.

As electromagnetic waves cannot propagate sufficiently far in water, underwater communication is mainly performed using either acoustics or optics. However, none of these technologies have been proven to be completely effective in every situation. Therefore, research in new underwater communication systems can still bring large benefits to a wide range of different underwater technologies.
During this project, a promising new type of underwater communication system based on electric fields has been investigated. While two subgroups have been working on the characterization of the communication channel and different modulation techniques, this thesis focuses on the hardware needed for optimal communication. Moreover, this hardware includes both a low-noise receiver and a high power transmitter. An analysis of different design options, the detailed design of one of these options and the validation of the design are given in this report. However, to get a complete overview of the designed communication system and its performance, it is recommended to also read the other two thesis reports.

Designing the future of work is a goal that is currently being tackled by both industry and academia. In a scenario where we have Human-Robot hybrid teams, it will be necessary for both human and robots to be aware of each other in their respective tasks. This thesis explores how specific robots (cobots - collaborative robots) can use Computer Vision-based methods for awareness of a human's presence, while using this data to influence the cobot's own behaviour.
After explorations of the Computer Vision field in regards to this problem, and selected approaches in the domain of Human Awareness for Human-Robot Interaction in literature, this thesis presents a proof of concept software/hardware system that, given all the apriori findings, implements simple demos that demonstrate both the feasibility and the suitability of a pure vision-based system for the problem of human awareness. It then analyses the strengths and weaknesses of the proposed system solution, ending with a road-map of recommendations for a following production prototype.

Mobile devices are getting increasingly powerful, becoming compatible
for an ever increasing set of functionality. Applications based around
neural networks however still have to offload parts of their computations
to the cloud since current Artificial Neural Networks (ANNs) are
still too computationally expensive for any practical standalone use in
energy constrained mobile devices. Developments in the next generation
of ANN: Spiking Neural Network (SNN), are expected to bring
neural networks directly to the edge. Even though SNNs are becoming
a reality, they can not (yet) effectively operate on raw sensory input
data. For this, a preprocessing algorithm can be used to extract low-level
features in an efficient way to boost the neural network efficiency.
A parallel can be found in biology with the cochlea that, for audio,
provides preprocessing for the brain. Recent research has shown that
an SNN is capable of reaching high classification accuracy when combined
with an biologically plausible audio preprocessing stage. To be
of interest for edge-computing it however also needs to be area and
energy efficient. This thesis will provide the first steps in researching
the optimal configuration of a specific audio preprocessing algorithm
by mapping its current software simulation to embedded hardware.
For this purpose the software simulation is analyzed and an efficient
hardware implementation is designed. For evaluation a prototype,
and its hardware constrained simulation, is developed and optimized.

This report focuses on the design and implementation of both a detection system and an enclosure, which are designed to be used in a quantum random number generator. These parts are designed to be manufactured using off-the-shelf components to make the quantum random number generator affordable and accessible to a completely new user-group that cannot afford and operate the currently existing alternatives for quantum random number generation. After implementing the designed systems it is found that although the output of the system is random, true-randomness cannot be guaranteed using off the shelf components, because of the interference of classical noise sources.

Recently, it has become popular to use Convolutional Neural Networks (CNNs) in embedded and portable devices. The popularity is based on their high accuracy rate in the field of Computer Vision (CV). However, CNNs are computationally intensive due to the convolutional layer, which accounts for over 90% of the operations. To overcome this problem, many researchers have exerted efforts to develop parallel and customised accelerators. Methods utilised in the accelerators range from bit optimisation to using fixed-point arithmetic, and to reducing the size of the network. Some researchers have also explored alternative computing paradigms such as Stochastic Computing (SC). The great advantage of SC is its ability to perform complex arithmetic with simple hardware. However, a major problem of SC is the trade-off between latency and accuracy. Thus, there have been several attempts to mitigate this factor, ranging from improving the generation of stochastic numbers to parallel bitstreams, to early terminations. This thesis proposes StoHej, a new SC multiplier design that combines stochastic bitstreams and complementary events. The multiplier has two input types, the first is the neural network feature value and the second is the weight value. The weight value determines how many iterations the computation requires. A complement event is utilised if the weight value is greater or equal to $0.5$ since the complement of the event yields a smaller number. Thus, the worst-case latency has been reduced from O(N) to O(N/2). The proposed multiplier was compared with a Conventional Stochastic Computer (CSC) multiplier and the BISC-MVM multiplier, which is the state-of-the-art for SC multipliers that uses an early termination mechanism. All multipliers were first tested in a software simulation in a general context. Accuracy and latency were measured in a software simulation. The results from these simulations showed a 3.2x speedup for the proposed design compared to BISC-MVM, with no increase in computational errors. Then, StoHej and BISC-MVM were tested in a CNN inference application with the MNIST dataset. The multipliers were used in a Multiply-Accumulate (MAC) array that was implemented on an FPGA. The results from the experiment show that StoHej had a 1.7x speedup and no loss in accuracy compared to BISC-MVM. StoHej's energy consumption was reduced by 40% when compared to BISC-MVM. The Area-Delay Product (ADP) of StoHej was 30% smaller than BISC-MVM. StoHej's Area-Delay-Energy Product is 2.3x smaller than the BISC-MVM multiplier.

Elliptic Curve Cryptography (ECC) performance is a major performance bottleneck when serving many VPN clients from a single server on a low-frequency FPGA softcore CPU. Using an area-efficient Elliptic Curve Point (ECP) multiplication accelerator core on the same FGPA, a much higher amount of clients can be served using the same FPGA chip. Using the accelerator core, the obtained speedup ranges from 1.6x in a suboptimal configuration up to 7x with a configuration that maximizes the use of ECC when connecting new clients to the server. In this optimal configuration, the total amount of clients that can be served by a single OpenVPN server increases from 80 in the base case, to 350 in the accelerated case.

Space has always been fascinating to humans, since the dawn of civilization. From the first astronomers and philosophers of ancient times, who looked at the night sky searching for answers, to the scientists and engineers of modern missions, commanding space probes to the edge of the solar system, space has always been at the epicenter of scientific discovery and human curiosity. From the launch of Sputnik 1 in 1957, to the robotic rovers exploring Mars, space missions have always relied on the latest technological advancements in order to enable physical or remote exploration of celestial bodies. Traditionally, designing a space computer required significant amount of resources, leading to designs with impressive radiation performance records. However, such designs were lacking computational performance, required years of development and as a result increased the total cost of the mission.

In recent years, the advent of CubeSats meant that access to space became available to a wider community of enthusiasts, researchers and private companies who were developing low-mass spacecraft made out of Commercial Off-The-Shelf components (COTS). These components however, were designed with the goal of maximizing performance and power, with little to no flight heritage. Several novel technologies were proposed in the field of error detection and mitigation, in an effort to bridge the gap between COTS processors and their radiation-hardened counterparts. Even though the commercial semiconductor industry has increased the reliability of its products by continuously improving their designs and processes, CubeSats or other low-mass spacecraft that use these components are still less reliable than their larger counterparts.

Given the aforementioned, this thesis aimed at exploring the latest developments in the field of space embedded systems and error detection techniques, in an effort to produce a software flow able to detect faults with increased compatibility across processor models. In order to accomplish this goal, the thesis was carried out at ARM Limited, as part of the Software Test Libraries (STL) team responsible for developing efficient assembly tests for detecting random faults. The Cortex-M55 CPU was chosen as the test-bed for this work, in order to develop STL routines for a reference module. TheMain Interface Unit (MIU) was chosen to act as the proof-of-concept, since it is an important module in every Cortex-M processor, interfacing the core with the main memory.

More specifically, a series of tests were developed for every major module within the MIU. The design started from the largest module first, which yielded a good trade-off between coverage and time. The tests comprised of efficient assembly routines designed to trigger specific memory access patterns, targeting different portions of logic each time. At the same time, a verification software flow was developed in order to test the newly designed routines against a multitude of possible configurations and initialization parameters. This activity was necessary to ensure that the developed software will be able to operate in a variety of end applications, either in the context of a Real-Time Operating System or baremetal application.

The developed STL tests were subjected to a series of fault simulations using a state-of-the-art hardware simulation tool called ZOIX. Permanent faults caused by accumulated damage were modeled as stuck-at-faults, whereas transient soft-errors were modeled as transient toggle faults. Determining an accurate fault injection interval, required knowledge of the radiation environment that a COTS-based mission would encounter. A state-of-the-art space simulation environment called SPENVIS was used in order to acquire metrics on selected reference missions on Low Earth Orbit and Geosynchronous Equatorial Orbit. This helped setting the upper limits on upset rates, which were in turn used during fault simulation to recreate realistic conditions.

The developed software tests exhibited solid performance in detecting permanent faults, while achieving promising results in transient fault simulations, given certain assumptions. A series of recommendations is given for future research work on the current framework, in an effort to learn from the challenges faced and tackle some of the identified limitations. Given certain assumptions, there is evidence to believe that STLs could be indeed used for random error detection in future CubeSat missions, without increasing the total cost disproportionately.

The Internet of Things (IoT) is expected to include billions of tiny devices that collect, process, and communicate sensory data. As of now, batteries power these devices. Batteries, however, are large, expensive, and short-lived - even the rechargeable ones wear out in a few years. Therefore, they are not a sustainable powering solution. Tiny battery-less devices promise a maintenance-free and environment-friendly alternative. They operate by harvesting energy from the environment. Ambient power, however, is marginal and unpredictable. This causes tiny energy-harvesting devices to operate intermittently, violating the requirements of many real-world applications.
This work presents an event-based command-recognition algorithm tailored towards battery-less sensors, taking into account the challenges of intermittent execution and the ultra-low-power hardware. Our algorithm achieves a 97% recognition accuracy with a ten-word vocabulary.

A variable speed AC motor drive, fed by a 3-phase AC supply, often consists of a 3-phase bridge diode rectifier, a DC link capacitor and a pulse width modulated inverter. Recently, a new type of capacitor known as film capacitor or slim capacitor has become popular for use in DC link. This capacitor has a lower value of capacitance and a longer life span than the conventional electrolytic capacitor. A film (slim) capacitor is advantageous over the electrolytic capacitor for use in the DC link because, for a low power motor, it results in a varying DC link voltage. This produces a less distorted grid current thereby improving the power factor. However, drives with slim DC link fed by a soft grid exhibits the tendency to oscillate at higher frequencies. This can be attributed to the LC resonance between the grid inductance and the small DC link capacitance, which results in significant but unwanted voltage ripples on the DC link. The unwanted harmonics affect the performance of the motor and the current drawn from the grid. As a result, the motor drive does not comply with the IEC 61000-3-2 harmonic standard. The objective of this project is to formulate, model and test a control algorithm to suppress the effects of the LC oscillations. This thesis proposes a novel compensation method that estimates the ideal DC link voltage without the unwanted ripples and feed-forwards the reconstructed DC link voltage to the motor drive algorithm, thereby altering the behavior of the motor drive to be more resistive such that the ripple gets damped. By doing so, the current drawn by the motor from the grid will have lesser harmonic content. Therefore, the power factor of the system will improve and the system will adhere to the harmonic standards.

Spiking Neural Networks have opened new doors in the world of Neural Networks. This study implements and shows a viable architecture to detect and classify blob-like input data. An architecture consisting of three parts a region proposal network, weight calculations, and the classifier is discussed and implemented. The region proposal network is build based on a blob detecting Laplacian of Gaussian function. The architecture is tested and verified on the Multi MNIST dataset that is generated based on the MNIST dataset that consists of handwritten digits. Results show that, on average, the region proposal network can locate the blobs in the input with an accuracy of within a single pixel distance from the ground truth. Two different ways of decoding the rate data coming from the region proposal network where discussed the Peak based decoder could propose regions even if these regions are situated closely together. A Center of Mass decoder is slightly more accurate than the Peak based decoder but at a higher computational cost and performance degradation when the regions are close together. The region proposal network at worst only accounts for 3.19% of inaccuracy. The implementation shows that the architecture is a viable way of detecting and classifying multiple objects within the input. The data shows that the region proposal network itself is a feasible way of detecting blob-like objects within its input.