Digital pre-distortion (DPD) is a well-established and highly effective technique for linearizing radio frequency power amplifiers. With the advent of 5.5G/6G base stations and Wi-Fi 7, DPD has become increasingly critical to support wideband signals and higher data rates. State-of-the-art DPD models predominantly leverage neural networks to process time-domain (TD) signals. While the TD-DPD enables point-to-point pre-distortion of TD signals, frequency-domain (FD) DPD requires the entire spectrum as input to generate time-domain outputs. This requirement results in a large number of input neurons and significantly increases computational complexity, thereby limiting the practical application of FD-DPD and hindering insights into frequency-dependent distortion characteristics. This paper introduces a lightweight frequency-domain (FD) neural network architecture incorporating a novel feature extraction method and integrate it with a TD-DPD model to develop an innovative Hybrid-DPD model. Evaluated on the OpenDPD platform with DPA_200MHz dataset, the Hybrid-DPD achieves simulated ACPR of -50.28 dBc, EVM of -45.30 dB and NMSE of -42.92 dB with 578 parameters. This performance surpasses that of the time-domain-only DPD with a comparable parameter count of486 by approximately 1 dB.

Eye tracking serves as a critical component across diverse areas of human-computer interaction (HCI) and healthcare applications, serving as a key enabler for intuitive and seamless user experiences. In HCI, eye tracking allows systems to detect users’ visual attention and gaze direction, facilitating natural interaction methods in augmented reality (AR), virtual reality (VR), and assistive technologies. In the healthcare domain, it is used for diagnosing and monitoring neurological disorders for patients. To be practical for deployment in wearable or embedded systems, eye tracking systems must deliver realtime performance while maintaining ultra-low power consumption. This requirement poses significant challenges in algorithm design and hardware implementation, especially when balancing accuracy, responsiveness, and energy efficiency. This thesis introduces JaneEye, an event-based eye tracking hardware accelerator optimized for ultralow latency and power consumption. The system is built around a lightweight, self-designed neural network architecture, in which a gated multilayer perceptron (MLP) and a novel convolutional Just Another Network (ConvJANET) layer play central roles in enabling efficient and accurate prediction. Despite having only 17.6K parameters, the proposed network maintains high prediction accuracy. Through software-hardware co-design strategies including quantization and nonlinear activation function approximation together with a new dataflow strategy that combines weight stationary and output stationary modes, the accelerator achieves remarkable performance. Based on post-layout simulation in GlobalFoundries 12LP-PLUS technolog, the JaneEye accelerator reaches an end-to-end latency of 0.5 ms (equivalent to 2000 FPS) while consuming just 18.9 μJ per frame operating at 400 MHz. To the best of our knowledge, this work demonstrates state-of-the-art trade-offs among accuracy, latency, and energy efficiency for event-based eye tracking, making it a strong candidate for integration into future AR/VR headsets and wearable healthcare devices.

As a crucial component, one common challenge of power amplifiers (PA) is the nonlinearity in the wireless communication system. Digital predistortion (DPD) is essential for mitigating nonlinearity in radio frequency (RF) power amplifiers, particularly for wideband applications. This thesis work aims to present the TCN-DPD model, a novel parameter-efficient architecture based on temporal convolutional networks (TCNs) to enhance the performance of PA. Therefore, the main problem should focused on the TCN-DPD model implementation with parameter efficiency. When TCN architecture was designed with several noncausal and dilated depthwise convolution layers and 1*1 convolution layers, optimized activation functions should be explored to complete the TCN architecture. By evaluating on the OpenDPD framework with the DPA_200MHz dataset, Hardswish, Tanh, SiLU, and GELU were considered by benchmarking different activations of TCN-DPD based on SIM- NMSE and SIM-ACLR metrics on average. Hardswish was confirmed in the later experiments as the optimized activation function in TCN architecture based on simulated results ACLR of -51.54 dBc and
NMSE of -44.61 dB. Since the TCN-DPD architecture was completed, this proposed model’s performance in PA and DPD benchmarks is desirable to be tested, and later experiments will use the same dataset and framework as the benchmark of activation function did. In PA benchmarking, the TCN model achieves SIM-NMSE -34.99 dB on average compared to other models, LSTM, GRU, RVTDCNN, VDLSTM, PNTDNN, and DGRU. This achievement shows the TCN architecture has a high potential to handle a range of dependencies efficiently in the DPD application system. Furthermore, DPD benchmarking is the main experiment in this thesis. Two architectures were selected as the pre-trained PA model: the DGRU and TCN models. When the pre-trained PA is fixed as the DGRU model, TCN-DPD demonstrates superior linearization performance with only 500 real-valued parameters, achieving averaged and simulated ACPRs of -51.58/-49.26 dBc (L/R), EVM of -47.52 dB, and NMSE of -44.61dB. The results are simulated ACPRs of -50.39/-50.01 dBc (L/R), EVM of -47.88 dB, and NMSE of -45.51 dB in average when the pre-trained PA model is TCN. Both DPD benchmarks include different DNN-DPD models, and TCN-DPD has superior performance in the comparison, especially the SIM-NMSE and SIM-EVM performance is significantly higher than other models when the pre-trained model is TCN. These results establish TCN-DPD as a promising solution for efficient wideband PA linearization. Moreover, the evaluation extended to DNN-DPD performance with various numbers of parameters ranging from 200 to 1000, where the TCN-200 model highlighted its effectiveness by showing impressive results in SIM-NMSE -41.27dB/-43.51dB(DGRU/TCN PA), achieving superior linearization performance while using significantly fewer parameters than existing deep neural network solutions, proving the TCN-DPD model’s parameters efficiency.
The research in this thesis conclusively demonstrates that TCNs can be implemented in DPD applications, providing more parameters efficiency, better performance, and robust PA linearization solutions, potentially setting a new alternative in DPD technology.

As wireless communication systems grow more complex, especially with the advent of 5G networks, the demand for efficient digital predistortion (DPD) techniques to improve the linearity and performance of power amplifiers (PAs) is increasing. Advanced neural network hardware accelerators like EdgeDRNN offer promising solutions to these challenges by enhancing computational efficiency and accuracy. This thesis provides a detailed evaluation of the EdgeDRNN hardware accelerator, which is applied by the OpenDPD network to tackle the common issues of computational complexity and parameter management that often impede DPD implementations. By employing high-level synthesis (HLS) for the linear layer within the EdgeDRNN model, the performance metrics can be improved. Through our research, we estimate the performance of the combined system, which has a latency of 6.50 microseconds and a throughput of 0.26 giga-operation per second. The study highlights EdgeDRNN’s performance and scalability, particularly in its ability to adapt to future wireless standards like 5G. However, the research also identifies some limitations on the performance, which sets a stage for future exploration. By designing and optimizing a new hardware accelerator for DPD, this work enables ultra-high-speed DPD solutions for next-generation wireless communication systems.

As communication capacity continues to expand, the application of deep neural networks (DNNs) for digital pre-distortion (DPD) has become increasingly prominent in addressing non-linearity issues in wideband power amplifiers (PAs). The advent of the fifth-generation (5G) era imposes higher requirements on DPD regarding frequency and latency. The integration of multiple-input multiple-output (MIMO) technology and micro base stations has driven the trend towards low-power, small-area DPD chips. This paper presents a high-performance, Gated Recurrent Unit (GRU)-based hardware architecture, characterized by high parallelism, and low resource consumption, enabling real-time signal processing by DPD. A novel method is proposed, employing quantization-aware training (QAT) with Hardsigmoid and Hardtanh functions to quantize the floating-point model in software. The optimized algorithm is implemented on hardware with inter-layer pipelining and retiming to optimize timing and increase clock frequency. Additionally, hardware-efficient linear functions, Hardsigmoid and Hardtanh, are utilized for activation functions to minimize hardware overhead. Experimental results demonstrate that hardware implementation achieves an Adjacent Channel Power Ratio (ACPR) of 49.48 dBc and an Error Vector Magnitude (EVM) of 46.05 dB, showin minimal degradation compared to the floating-point model (49.58 dBc/ 46.70 dB). Simulated under 22nm CMOS technology, the DPD chip, operating at 2GHz, occupied an area of 0.047 mm2 and is capable of handling signals with bandwidth up to 70 MHz. The highest throughput reaches 256.5 GOp/s while the power efficiency reaches 1.3154 TOp/s/W.

Keyword spotting (KWS) is an essential component of voice recognition services on smart devices. Its always-on characteristic requires high accuracy and real-time response. Also, low power consumption is another key demand for KWS devices. In previous research, neural networks have become popular for KWS tasks for their accuracy compared to traditional machine learning technologies. Among classical neural networks like recurrent neural networks (RNNs) and convolutional neural networks (CNNs), temporal convolutional networks (TCNs) have begun to catch attention recently. Moreover, studies related to sparsity are always an efficient method to deal with the growing model size issue for modern neural network designs. As a potential solution, in this work, a TCN model is trained for KWS on the Google Speech Command V2 dataset and achieves an accuracy of 94.1\%. Based on that, two different sparsity are applied to the TCN model. One is temporal sparsity. By creating a Delta convolution layer, the Delta temporal convolutional network (DeltaTCN) achieves an accuracy of 93.6\% with a 72\% reduction in floating-point operations (FLOPS) compared to the original TCN model. Another is structural weight sparsity. By creating sparsity on the weight matrix of each convolution layer, the structural sparse temporal convolutional network (SSPTCN) achieves 93.6\% accuracy with a 70\% reduction in FLOPs and a 39\% reduction in parameters.

With the advancement of 5G/6G radio networks, the demand for high-performance power amplifiers (PAs) with clean spectra and compact constellations has increased significantly. To address these challenges, Artificial Intelligence (AI)-based digital predistortion (DPD) has emerged as a promising approach to linearize radio-frequency (RF) PAs. However, existing state-of-the-art AI-based architectures rely on computationally expensive online feature extraction to achieve satisfying linearization performance, resulting in complicated algorithm data paths and difficulty in energy-efficient hardware implementation. This thesis proposes a new deep recurrent neural network (RNN)-based DPD architecture, called Skip Gated Recurrent Unit (SGRU), with precise offline baseband signal feature extraction to bypass the need for complex online feature extraction while still maintaining high linearization performance. The proposed RNN architecture employs the end-to-end (E2E) learning framework to implement an efficient DPD model. By combining the offline feature extraction and E2E framework, we achieved a more streamlined and faster training method for wideband RF power amplifier (PA) DPD. With a simplified neural network architecture and fewer parameters, our approach utilizes 394 parameters to achieve an adjacent channel power ratio (ACPR) (lower/upper) of -45.16/-44.31 dBc for 100 MHz orthogonal frequency division multiplexing (OFDM) signal, ACPR (lower/upper) of -38.44/-42.09 dBc for 200 MHz OFDM signal. Compared to previous state-of-art phase gated just-another-network (PG-JANET) [1] and decomposed vector rotation just-another-network (DVR-JANET) [2], our approach has better ACPR and error vector magnitude (EVM) performance with parameters around 400. Compared to vector decomposition long-short-term memory (VDLSTM) [3], our approach achieves a better lower/upper band balance.

Voice activity detection (VAD) is the prevailing approach to extracting meaningful speech information from the pervasive noise found in the physical environment. Presently, deep neural networks (DNN) are widely employed as the classifier component in Voice Activity Detection (VAD) systems. However, conventional deep neural networks, like fully connected (FC) deep neural networks, encounter the challenge of excessive computational complexity. This heightened complexity can result in diminished computing efficiency, unnecessary utilization of hardware resources, and redundant power consumption. To address the inefficiency issue from computational complexity, this study introduces a novel neural network architecture named DeltaFC. This architecture attains an operation time latency of less than 1 ms for each 30ms voice segment, resulting in a 54% reduction in latency compared to the baseline fully connected (FC) model. In software design, this study tackles the issue by compressing and encoding time-series information using the Delta algorithm, with the objective of introducing temporal sparsity. Based on the software results, the neural network surpasses both the baseline fully connected (FC) and LSTM models in AUC (area under the curve), with accuracy at a lightweight parameter scale. In hardware design, this study reproduces the neural network software design into FPGA hardware RTL design, implementing a lightweight digital IP core. This digital IP core accelerates neural network operations in hardware by the deployment of Delta and CSR algorithms. Compared with not introducing temporal sparsity, the computing efficiency increases by approximately 85% with 0.5% loss in accuracy. This substantiates that within the domain of lightweight neural networks containing fewer than 30,000 parameters, the DeltaFC network proposed in this study is more suitable for Voice Activity Detection (VAD) when compared to fully connected (FC), LSTM, and other baseline network architectures.

Ultra-low power Edge AI hardware is in increasing demand due to the battery-limited energy budget of typical Edge devices such as smartphones, wearables, and IoT sensor systems. For this purpose, this Thesis introduces an ultra-low power event-driven SRAM-based Compute In-Memory (CIM) accelerator optimized for inference of Binary Spiking Neural Networks (B-SNNs). In this Thesis, a custom-designed 3nm SRAM cell is developed, with up to four read ports to improve inference performance and one transposable read/write port for efficient on-chip learning functionality. The event-based nature of SNNs is exploited to minimize the computation and memory cost. The design benefits from technology scaling of fully digital design by synthesizing the accelerator in the imec 3nm FinFET technology node. The proposed accelerator's performance is evaluated by running MNIST inference at 97.6% accuracy, achieving an impressive throughput of 44M inferences/s at 607 pJ/inference (3.2 fJ per synaptic operation) while running at 29 mW. The results demonstrate that the proposed accelerator provides an energy-efficient and high-performance solution for inference of Binary SNNs, opening up new possibilities for Edge AI applications.