The rapid growth of wireless data traffic is driving 6G networks toward higher data rates, lower latency, and wider bandwidths. Power amplifiers (PAs) must operate efficiently and linearly over extreme bandwidths, but traditional polynomial-based digital predistortion (DPD) techniques struggle with wideband signals due to increased computational complexity and memory requirements.
Neural network (NN)-based DPD offers a promising alternative, modeling complex PA nonlinearities with improved flexibility and linearization performance. Existing NN-based approaches, mostly using recurrent neural networks, face limitations in parallelization, making them unable to satisfy the throughput requirements of wideband signals.
This thesis introduces a hardware-aware Phase-Normalized Time-Delay Neural Network DPD architecture, optimized for FPGA and ASIC implementation. The design balances the high linearization performance and throughput requirements with low power consumption and minimal silicon area. The study used algorithm–hardware co-design strategies to create a viable NN-based DPD solution for next-generation wireless transmitters. The research is limited to simulated measurements, with no physical measurements being done.
Simulated results show that the PNTDNN achieves strong linearization for both narrowband and wideband signals, with FPGA and ASIC implementations supporting real-time processing of 20 MHz and 400 MHz base-band signals, respectively. The architecture demonstrates scalability, energy efficiency, and reprogrammability, providing a practical solution for next-generation 6G transmitters and bridging the gap between advanced NN-based DPD algorithms and hardware feasibility.
Simulated results demonstrate that the PNTDNN achieves strong linearization performance for both narrowband and wideband signals. For a 400 MHz baseband bandwidth signal, it attains –36.3 dB EVM, –38.5 dB NMSE, and –45.6 dB ACPRAVG with approximately 1000 parameters, while for a 20 MHz baseband bandwidth signal, it achieves –54.0 dB EVM, –48.2 dB NMSE, and –59.4 dB ACPRAVG using only 64 parameters. The FPGA implementation for the 20 MHz dataset achieves 7.5× oversampling at 170 MHz clock frequency and throughput, using 405 mW power. The ASIC implementation for the 400 MHz dataset achieves 2× oversampling at 1.2 GHz clock frequency and throughput, with an area of 0.451 mm2 using 893 mW power. Both the FPGA and ASIC implementations allow power optimization via unstructured pruning, with the FPGA having hardcoded weights and biases and the ASIC having reprogrammable weights and biases.