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document
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Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f <sup>3</sup> ) and thermal (1/f <sup>2</sup> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...
journal article 2019
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document
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Chen, Peng (author), Huang, Xiongchuan (author), Chen, Y. (author), Wu, Lianbo (author), Staszewski, R.B. (author)
To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order &#x0394;&#x03A3; time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...
journal article 2018
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