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Concept of Spatially-Divided Deep Reactive Ion Etching of Si using Oxide Atomic Layer Deposition in the Passivation Cycle

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Author: Roozeboom, F. · Kniknie,B. · Knaapen, R. · Smets, M. · Illiberi, A. · Poodt, P. · Dingemans,G. · Keuning, W. · Kessels, W.M.M.
Type:article
Date:2012
Publisher: ECS
Place: Eindhoven
Source:4th Electronics System Integration Conference (ESTC 2012), Amsterdam, Sept. 17-20, 2012
series:
ECS Transactions
Identifier: 483374
doi: doi:10.1109/ESTC.2012.6542052
Article number: 2756
Keywords: Physics · Industrial Innovation · Mechatronics, Mechanics & Materials · TFT - Thin Film Technology · TS - Technical Sciences

Abstract

Conventional Deep Reactive Ion Etching (DRIE) is a plasma etch process with alternating half-cycles of 1) Si-etching with SF6 to form gaseous SiFx etch products, and 2) passivation with C4F8 that polymerizes as a protecting fluorocarbon deposit on the sidewalls and bottom of the etched features. In this work we report on a novel alternative and disruptive technology concept of Spatially-divided Deep Reactive Ion Etching, S-DRIE, where the process is converted from the time-divided into the spatially divided regime. The spatial division can be accomplished by inert gas bearing ‘curtains’ of heights down to ~20 μm. These curtains confine the reactive gases to individual (often linear) injection slots constructed in a gas injector head. By horizontally moving the substrate back and forth under the head one can realize the alternate exposures to the overall cycle. Another improvement in the spatially divided approach is the replacement of the CVD-based C4F8 passivation steps by ALD-based oxide (e.g. SiO2) deposition cycles. The method can have industrial potential in cost-effective creation of advanced 3D interconnects (TSVs), MEMS manufacturing and advanced patterning, e.g., in nanoscale transistor line edge roughness (LER) using Atomic Layer Etching.