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A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS

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Author: Soer, M. · Klumperink, E. · Nauta, B. · Vliet, F. van
Type:article
Date:2012
Source:59th International Solid-State Circuits Conference, ISSCC 2012, 19-23 February 2012, San Francisco, CA, USA, 55, 174-175
Identifier: 460452
Keywords: Physics · Defence Research · Defence, Safety and Security · Physics & Electronics · RT - Radar Technology · TS - Technical Sciences

Abstract

Phased arrays in CMOS for consumer communication bands aim to enhance receiver performance by exploiting beamforming with antenna arrays. Sensitivity increases with the number of antenna elements through array gain and interferers can be cancelled through the spatial filtering of the beam pattern [1]. For the latter, the linearity of the receiver before the beamforming summing point becomes a bottleneck as interferers are not cancelled yet. Phase shifting in the LO domain reduces the complexity in the signal path and enables the use of linear signal blocks, but has high requirements on the multiphase LO generation [2]. On the other hand, a switched-capacitor phase shifter can be very linear, but is limited by the linearity of the necessary input matching and element summing g m-stages [3]. This paper proposes a fully passive phased-array receiver front-end which implements impedance matching, phase shifting and element summing with only switched-capacitor stages for a high linearity. © 2012 IEEE.