A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

Wang, Zhongkai (University of California)
Choi, Minsoo (Samsung Semiconductor)
Wright, John (University of California)
Lee, Kyoungtae (University of California)
Liu, Zhaokai (University of California)
Yin, Bozhi (University of California)
Han, Jaeduk (Hanyang University)
Du, S. (TU Delft Electronic Instrumentation)
Alon, Elad (University of California)

2022

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

PLL
sub-sampling
ring oscillator
hybrid
PLL generator

http://resolver.tudelft.nl/uuid:06f907ea-7cbb-46bb-863f-87229532e41c

https://doi.org/10.1109/ISCAS48785.2022.9937615

IEEE, Danvers

2023-07-01

978-1-6654-8486-2

Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS)

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022-05-27 → 2022-06-01, Austin, United States

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Institutional Repository

conference paper

© 2022 Zhongkai Wang, Minsoo Choi, John Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, S. Du, Elad Alon