Print Email Facebook Twitter Balanced ternary addition using a gated silicon nanowire Title Balanced ternary addition using a gated silicon nanowire Author Mol, J.A. Van der Heijden, J. Verduijn, J. Klein, M. Remacle, F. Rogge, S. Faculty Applied Sciences Department QN/Quantum Nanoscience Date 2011-12-29 Abstract Ternary logic has the lowest cost of complexity, here, we demonstrate a CMOS hardware implementation of a ternary adder using a silicon metal-on-insulator single electron transistor. Gate dependent rectifying behavior of a single electron transistor (SET) results in a robust three-valued output as a function of the potential of the single electron transistor island. Mapping logical, ternary inputs to the three gates controlling the potential of the single electron transistor island allows us to perform complex, inherently ternary operations, on a single transistor. Subject addersCMOS logic circuitselemental semiconductorslogic gatesrectificationsiliconsingle electron transistorsternary logic To reference this document use: http://resolver.tudelft.nl/uuid:416bdd1f-5264-4c1c-9161-13f1128290d8 DOI https://doi.org/10.1063/1.3669536 Publisher American Institute of Physics ISSN 0003-6951 Source http://link.aip.org/link/doi/10.1063/1.3669536 Source Applied Physics Letters, 99 (26), 2011 Part of collection Institutional Repository Document type journal article Rights (c) 2011 The Author(s)American Institute of Physics Files PDF ApplPhysLett_99_2631091.pdf 606.57 KB Close viewer /islandora/object/uuid:416bdd1f-5264-4c1c-9161-13f1128290d8/datastream/OBJ/view