Accelerating Software Pipelines Using Streaming Caches

Accelerating Software Pipelines Using Streaming Caches

Yanik, K.I.M.

Wong, S. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2016-12-12

The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of a data-path, where a task is split in stages which are distributed over several functional units who work in parallel. In software the concept of pipelines does exist, but mostly speaks about data-flows as here stages do not operate in parallel. This thesis proposes a step towards making this a possibility by mapping software pipelining on heterogeneous multi-core systems. This work documents the design, implementation and verification of a hybrid write-back and streaming cache scheme that aims to cut down overhead of inter-context and inter-core data communication, with the idea of allowing software pipelines to map stages over cores in the same microprocessor with different functional units, in order to fine-tune this mapping. A prototype design is first implemented in a high level behavioral simulator, after which it is implemented in VHDL, tested functionally to conform to a test-suite and a set of testing pipelines developed for this project separately. The VHDL design is implemented on the ML605 Virtex-6 platform, and in its current state conforms to all test-cases but not yet the pipelines, and a slight slow-down is measured in practice. Even though the prototype currently increased the run-time of a customly developed benchmarking pipeline from 3.3928 * 10^-4 seconds to 3.7858 * 10^-4 seconds, there is room for improvement and it enables more research in a new direction of transparently core-to-stage mapped software pipelines, which we define as horizontal software-pipelining, as opposed to traditional software pipelines who still execute code sequentially, hence vertically.

ρ-VEX
FPGA
Streaming
Processor
Cache
Pipeline
VLIW

http://resolver.tudelft.nl/uuid:81232e85-5c72-4b02-8cfc-462b4996b633

Student theses

master thesis

(c) 2016 Yanik, K.I.M.