A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC

A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC

Elumalai, I.

Long, J. (mentor)
Bult, K. (mentor)
Ward, C. (mentor)

Electrical Engineering, Mathematics and Computer Science

Electronics

Microelectronics

2013-08-30

Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC causes glitches on the reference voltage, and the buffer has to be fast enough to recover such transients to 1/2 LSB precision in every bit cycle. Such stringent requirements entail an immensely capable buffer for high-speed, high-resolution converters. One obvious olution circumventing the active buffer is to use a stand-alone capacitor that holds the reference voltage during SAR evaluation. This solution accompanies, besides good power efficiency, excellent DAC settling speed and noise properties, thereby greatly helping the ADC FoM. Reducing the capacitance of the stand-alone capacitor for chip area concerns brings in code-dependent errors on the reference, leading to heavy distortion. This project implements an area-conscious, capacitance-based reference buffer scheme for a 14b-linear, 100 MS/s SAR-assisted pipeline ADC in 28 nm CMOS. With moderately-valued capacitances, two elaborate calibration techniques are proposed that help to suppress the reference-induced distortion to less than 84 dB, effectively not degrading the SNDR. Designed for 12-bit SNR, the prototype ADC with the implemented reference scheme consumes 1.81 mW and achieves a Schreier FoM of 175.5 dB.

ADC
SAR
charge redistribution
reference buffer
high speed
low power

http://resolver.tudelft.nl/uuid:8b94e22b-cd51-407c-af86-9c2389f20e4c

2014-09-20

Student theses

master thesis

(c) 2013 Elumalai, I.