A high-resolution self-timed zero-crossing-based Incremental ?? ADC

A high-resolution self-timed zero-crossing-based Incremental ?? ADC

Karykis, G.

Pertijs, M.A.P. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Microelectronics

2015-05-27

This thesis discusses the d es ign and verification of a high-resolution self-timed incremental ?? ADC. The first self-timed incremental ?? ADC was presented by C.Chen et.al at ISSCC 2013 and this work targets to improve the resolution, linearity and energy-efficiency of a self-timed ADC. Unlike conventional ?? ADCs, a self -timed ADC is capable of arranging the timing itself an d do es not rely on a dedicated clo ck, saving energy and reducing system complexity. This work is tailored for energy-constrained integrated sensor interfaces, where resolution and linearity requirements are often above 16-bit. For the implementation of the self-timed ADC, the knowledge of the charge-transfer completion of the switched-capacitor integrators of the lo op-filter is necessary for the generation of the self-timed control signals. Zero- crossing-based (ZCB) switched-capacitor integrators were employed b efore in the design of the self-timed I?? ADC because the knowledge of the end of the charge-transfer is available. Th is thesis focuses on the systematic noise and linearity design of the first ZCB integrator of the self-timed ADC, building on the implementation of C.Chen et.al (ISSCC 2013), wh ich is the state-of-the-art ?? ADC design that is employing comparator-based or zero-crossing-based switched capacitor (CBSC/ZCBSC) circuits up to now. An improved prototype chip of self-timed in cremental ?? ADC was implemented in NXP 1P 5M 0.16µm CMOS process. A second-order single-ended ?? modulator was designed accordingly and verified using pre-layout and post-layout simulations. The results of these simulations show that the improved prototype achieves resolution of approximately 16.7-bit, linearity of 1LSB with respect to 17-bit, when the modulator is operating for 1000 incremental cycles. The conversion time is less than 1.01ms, while the chip consumes less than 26µA from a 1V supply. This performance corresponds to a Schreier FOM of the ADC of 168.8dB, which is the best among CBSC/ZCB ?? ADCs and fairly close to the state-of-the-art of OTA-based ADCs for Instrumentation & Measurement or audio applications.

energy-efficient
high-resolution
incremental ?? ADC
self-timed
zerocrossing-based integrator

http://resolver.tudelft.nl/uuid:98bbf309-c0cd-4c7e-be40-6333d5427c9b

Student theses

master thesis

(c) 2015 Karykis, G.