Hardware Components for Real-Time Stereo Matching: Acceleration of 3D HD TV with FPGAs

Hardware Components for Real-Time Stereo Matching: Acceleration of 3D HD TV with FPGAs

Yeh, H.C.

Lafruit, G. (mentor)
Kuzmanov, G.K. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

Embedded Systems

2011-10-27

In recent 3D TV market, the technologies addressing to the applications such as stereoscopic depth scaling, glass-free 3D display, and Free Viewpoint TV are getting more attentions. A low-cost solution that can synthesize intermediate views from stereoscopic input contents(left and right camera views) is strongly needed. To render the interpolated views, the depth information of the left and right views are commonly-used in view synthesis algorithm. Therefore, this thesis researches stereo matching algorithms, which generate disparity maps. We implement a state-of-the-art semi-global stereo matching algorithm(dynamic programming and cross based) with FPGA. Our solution also concerns several aspects include disparity map/sequences quality, hardware cost, and real-time performance. Afterward the stereo matching engine design is integrated into IMEC's 3D TV SoC prototype. Several peripheral components, include color space converters, video I/O adaptors and a dedicated memory hierarchy, are developed for supporting both stereo matching and view synthesis engines. Finally, the SoC prototype is evaluated with EP3SL150 FPGA chip. So far it can process dual channel XGA video format (1024x768 @ 60 FPS) in real-time performance and render an acceptable synthesized view quality for depth scaling application. This design shows a promising solution for the 3D TV market.

Stereo Matching
Temporal Consistency
Memory Architecture
Depth Map Coding
Real-Time
FPGA
SoC

http://resolver.tudelft.nl/uuid:9c328616-3b4e-4890-9ea6-7a4c2ab3a2bc

2012-04-24

Student theses

master thesis

(c) 2011 Yeh, H.C.