Design-time and Run-time Reconfigurable Clustered ?-VEX VLIW Softcore Processor

Design-time and Run-time Reconfigurable Clustered ?-VEX VLIW Softcore Processor

Reda, M.B.

Wong, J.S.S.M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Embedded Systems

2014-08-27

The ?-VEX processor is a parameterized reconfigurable Very Large Instruction Word (VLIW) softcore processor. It can be reconfigured in the issue-width, number and type of functional units (FUs), width of memory buses and number of registers in the multi- ported register file. The current design of the ?-VEX processor supports single cluster processor organization. The design also provides run-time dynamic reconfigurability between different processor architectures. As the issue-width of the processor increases, the number of read and write ports from the FUs to the register file increases which enlarges its area utilization. This increase in the number of read and write ports is not scalable with the interconnect wires available in the current IC technology. From literature, we know that clustering the FUs of the processor and splitting up the register file into a smaller subsets significantly reduces the area overhead and power consumption. In this thesis, we have developed all the necessary hardware and software components to enable the design-time and run-time reconfigurable ?-VEX processors to support clustered organization. Those development are the design and implementation of inter- cluster communication FUs, inter-cluster path and local register file per cluster and the adaptation of the compiler toolchain. As an inter-cluster communication model (ICC), copy operation and dedicated issue slot ICC model are implemented. The cycle count and total operations of different benchmark applications are measured and analyzed on the clustered organization of ?-VEX processors. The cycle count for most of the benchmarks is higher in clustered organization except for applications with high instruction level parallelism such as matrix and adpcm. A speedup of 3.04× is achieved by matrix benchmark. On the other hand, an increase in code size of the benchmark applications is measured for the clustered processor by a maximum of 38%. The area utilization of the 4-issue and 8-issue design-time reconfigurable ?-VEX processors are significantly reduced by up to 74% by clustering them into two clusters. In addition, a speedup of 1.55× is obtained on the clock frequency of the processor. Similarly, the run-time reconfigurable clustered ?-VEX processor occupies 61.3% less area, consumes up to 41.6% less dynamic power than the single clustered processor and has a reduced energy delay product (EDP).

reconfigurable processor
clustered organization
run-time reconfigurable processor
multi cluster VLIW

http://resolver.tudelft.nl/uuid:ad113f9e-b3d0-4284-8229-3091764dc69b

Student theses

master thesis

(c) 2014 Reda, M.B.