Print Email Facebook Twitter Hierarchical verification of VLSI artwork Title Hierarchical verification of VLSI artwork Author Annevelink, J. Dewilde, P. Van Leuken, T.G.R.M. Fokkema, J.T. Date 1984 Subject circuit-layout-CAD VLSI- augmented-cell-instance VLSI-artwork layout-verification hierarchical-verification-techniques stateruler-scan-algorithm hierarchical-design-rule-checking circuit-extraction To reference this document use: http://resolver.tudelft.nl/uuid:f4fae4f6-43f9-4c3b-b2c2-189bcde24f7b Publisher IEEE, New York, NY, USA Source 1984-IEEE-International-Symposium-on-Circuits-and-Systems.-Proceedings-Cat.-No.-84CH1993-5.1984: 461-4 vol.2 USA Conference-Paper IEEE; Concordia Univ, 1524. (1984) Part of collection Institutional Repository Document type conference paper Files PDF 866379.pdf 358.4 KB Close viewer /islandora/object/uuid:f4fae4f6-43f9-4c3b-b2c2-189bcde24f7b/datastream/OBJ/view