Title
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array
Author
Escuin, Carlos (IMEC; Universidad de Zaragoza)
García-Redondo, Fernando (IMEC)
Zahedi, M.Z. (TU Delft Computer Engineering)
Ibáñez, Pablo (Universidad de Zaragoza)
Monreal, Teresa (Universitat Politecnica de Catalunya)
Viñals, Victor (Universidad de Zaragoza)
Llabería, José María (Universitat Politecnica de Catalunya)
Myers, James (IMEC)
Ryckaert, Julien (IMEC)
Biswas, Dwaipayan (IMEC)
Catthoor, Francky (IMEC)
Date
2023
Abstract
This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.
Subject
Compute in Memory
NVM
Memristor
MRAM
Convolutional Neural Networks
Machine Learning
To reference this document use:
http://resolver.tudelft.nl/uuid:49afef90-c5a0-4be5-ab5e-b0de0770755b
DOI
https://doi.org/10.1109/ICECS58634.2023.10382874
Publisher
IEEE, Piscataway
Embargo date
2024-07-10
ISBN
979-8-3503-2650-5
Source
Proceedings of the 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Event
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2023-12-04 → 2023-12-07, Istanbul, Turkey
Bibliographical note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Part of collection
Institutional Repository
Document type
conference paper
Rights
© 2023 Carlos Escuin, Fernando García-Redondo, M.Z. Zahedi, Pablo Ibáñez, Teresa Monreal, Victor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor