An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

Wang, Zhongkai (University of California)
Choi, Minsoo (Samsung Semiconductor)
Lee, Kyoungtae (University of California)
Park, Kwanseo (University of California)
Liu, Zhaokai (University of California)
Biswas, Ayan (University of California)
Han, Jaeduk (Hanyang University)
Du, S. (TU Delft Electronic Instrumentation)
Alon, Elad (University of California)

2022

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

28 nm
4:1 multiplexer (MUX)
Berkeley Analog Generator (BAG)
clock distribution
four-level pulse-amplitude modulation (PAM-4)
pulse generator
quarter-rate
SerDes
transmitter (TX)
wireline

http://resolver.tudelft.nl/uuid:c1053df6-a596-4e7d-adab-b2d5ffc93c38

https://doi.org/10.1109/JSSC.2021.3109562

0018-9200

IEEE Journal of Solid State Circuits, 57 (1), 21-31

Institutional Repository

journal article

© 2022 Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, S. Du, Elad Alon