Dependability of Future Edge-AI Processors: Pandora’s Box

Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs

Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs

Device-Aware Test for Back-Hopping Defects in STT-MRAMs

Device-Aware Test for Ion Depletion Defects in RRAMs

Online Fault Detection and Diagnosis in RRAM

Characterization and Test of Intermittent Over RESET in RRAMs

Device Aware Diagnosis for Unique Defects in STT-MRAMs

Hierarchical Memory Diagnosis

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Using Hopfield Networks to Correct Instruction Faults

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Structured Test Development Approach for Computation-in-Memory Architectures

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Recent Trends and Perspectives on Defect-Oriented Testing

Improving the Detection of Undefined State Faults in FinFET SRAMs

Intermittent Undefined State Fault in RRAMs

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs