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Ahmad, T. (author), Al-Ars, Z. (author), Hofstee, H.P. (author)
Background Recently many new deep learning–based variant-calling methods like DeepVariant have emerged as more accurate compared with conventional variant-calling algorithms such as GATK HaplotypeCaller, Sterlka2, and Freebayes albeit at higher computational costs. Therefore, there is a need for more scalable and higher performance workflows of...
review 2021
document
Ahmad, T. (author), Ahmed, N. (author), Al-Ars, Z. (author), Hofstee, H.P. (author)
Background: Immense improvements in sequencing technologies enable producing large amounts of high throughput and cost effective next-generation sequencing (NGS) data. This data needs to be processed efficiently for further downstream analyses. Computing systems need this large amounts of data closer to the processor (with low latency) for...
journal article 2020
document
van Dam, Laurens (author), Peltenburg, J.W. (author), Al-Ars, Z. (author), Hofstee, H.P. (author)
The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors...
conference paper 2019
document
Chen, Jianyu (author), Al-Ars, Z. (author), Hofstee, H.P. (author)
In this paper, we present the design in reconfigurable logic of a matrix multiplier for matrices of 32-bit posit numbers with es=2 [1]. Vector dot products are computed without intermediate rounding as suggested by the proposed posit standard to maximally retain precision. An initial implementation targets the CAPI 1.0 interface on the POWER8...
conference paper 2018
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