A Low Power System-on-Chip with Memory Stacked on Top of Logic

This work introduces a low-power Cortex-M0+ based computing platform for battery-powered, embedded applications. Voltage stacking is used to save power by recycling charge through a power domain between 0V and Vdd, and a power domain stacked on top of it between Vdd and 2Vdd. The technique enables connecting chips of the future directly to the...

A Low Power 10-bit SAR ADC in a 45nm CMOS process

In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the conventional 2^N , thus decreasing the DAC area and the DAC...