Fault tolerance on the ?-VEX processor

Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a...

Task Scheduling for Adaptive Reconfigurable VLIW Multicore Processors

Embedded Reconfigurable Architectures (ERA) is a project with the objective to design a platform that combines reconfigurable computing and network elements which can adapt on-the-fly their composition, organization and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given...

Porting Linux to the rVEX reconfigurable VLIW softcore

This thesis describes the design and implementation of an FPGA-based hardware platform based on the rVEX VLIW softcore and the adaption of a Linux 2.0 no_mmu kernel to run on that platform. The rVEX is a runtime reconfigurable VLIW softcore processor. It supports various configurations that allow programs to run faster or more efficient. The...

Interfacing the ?-VEX with the µBlaze processor

Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a result the performance gap of processors build on FPGA technology compared to Semi-custom ASIC technology is decreasing. The down side of...

Fingerprint Verification on the VEX Processor

The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...