ρ-VEX ASIC: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.<br/>A fully automatic scripted flow is described, constructing an...