Hardware acceleration of artificial X-ray image generation

X-ray imaging systems play an important role in the diagnostic process of various medical conditions. Generating an accurate artificial X-ray image has multiple advantages. It allows for flexible configurations during generation. The resulting images can reduce testing time and cost, help the training of surgeons, and increase the amount of data...

Low-cost multi-core on-chip learning schemes

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network...

Neural network partitioning for resource-limited environments

The demand for implementing neural networks on edge devices has rapidly increased as they allow designers to move away from expensive server-grade hardware. However, due to the limited resources available on edge devices, it is challenging to implement complex neural networks. This study selected the Kria SoM KV260 hardware platform due to its...

A New Logarithmic Quantization Technique and Corresponding Processing Element Design for CNN Accelerators

Convolutional Neural Networks (CNN) have become a popular solution for computer vision problems. However, due to the high data volumes and intensive computation involved in CNNs, deploying CNNs on low-power hardware systems is still challenging.<br/>The power consumption of CNNs can be prohibitive in the most common implementation platforms:...

A Low-speed, Low-acceleration Controller for Cost-effective Reaction-wheels: Design, Simulation & Implementation

With the requirements for CubeSats increasing, a push towards utilizing high­performance equipment has never been greater. Incorporating these equipment in an environment that is cost­, space­ and power­constrained, is challenging. Simultaneously, high­performance equipment require high pointing­accuracy and low­jitter. This thesis proposes the...

Integration of a convolutional neural network for speech-to-text recognition in an FPGA compiler flow

Deep Neural Network (DNNs) have increased significantly in size over the past decade. Partly due to this, the accuracy of DNNs in image classification and speech recognition tasks has increased as well. This enables a great potential for such models to be applied in real-world applications. However, due to their size, the compute and power...

Exploring the Limits of Query Pushdown for SQL Acceleration on FPGAs

There has been an increasing interest in moving computation closer to storage in recent years due to significant improvements in memory technology. FPGAs were proven to be an exciting candidate for accelerating database workloads since they provide an energy-efficient, reconfigurable and high-performance computation platform. Therefore, FPGAs...

FPGA Based Deep Learning Accelerator for RF Applications: A Design Framework

Recently, interest in the use of deep learning technology for RF applications has increased. However, many of these studies are focused on developing deep learning models for a particular RF application. Therefore this master thesis focuses on the implementation of these kinds of deep learning models by using FPGAs such that these deep learning...

Ultra low latency deep neural network inference for gravitational waves interferometer: *

Low latency Convolutional Neural Network (CNN) inference research is gaining more and more momentum for tasks such as speech and image classications. This is because CNNs have the ability to surpass human accuracy in classication of images. For improving the measurement setup of gravitational waves, low latency CNNs inference are researched. The...

Dataflow Hardware Design for Big Data Acceleration Using Typed Interfaces

Recent trends in large-scale computing demonstrate continuous growth in the need for raw processing performance. At the same time, the slowdown of vertical scaling pushes the industry towards more energy-efficient heterogeneous architectures. With the appearance of FPGAs in the cloud and data centers, a new architecture is offered for offloading...

An Elliptic Curve Cryptography Acceleration Core for OpenVPN on an FPGA Softcore

Elliptic Curve Cryptography (ECC) performance is a major performance bottleneck when serving many VPN clients from a single server on a low-frequency FPGA softcore CPU. Using an area-efficient Elliptic Curve Point (ECP) multiplication accelerator core on the same FGPA, a much higher amount of clients can be served using the same FPGA chip. Using...

Optimizing Memory Mapping for Dataflow Inference Accelerators: Efficient Memory Utilization on FPGAs

Convolutional Neural Network (CNN) inference has gained a significant amount of traction for performing tasks like speech recognition and image classification. To improve the accuracy with which these tasks can be performed, CNNs are typically designed to be deep, encompassing a large number of neural network layers. As a result, the...

High Throughput Sorting on FPGAs using High Bandwidth Memory

In this thesis we explore the acceleration of sorting algorithms on FPGAs using high bandwidth memory (HBM). The target application is an FPGA as an accelerator in an OpenCAPI enabled system, that enables the accelerator to access main memory of the host at a bandwidth of 25 GB/s for either read or write. We explore under what read and write...

High-Throughput Big Data Analytics Through Accelerated Parquet to Arrow Conversion

With the advent of high-bandwidth non-volatile storage devices, the classical assumption that database analytics applications are bottlenecked by CPUs having to wait for slow I/O devices is being flipped around. Instead, CPUs are no longer able to decompress and deserialize the data stored in storage-focused file formats fast enough to keep up...

VHDL Implementation of 4096-bit RNS Montgomery Modular Exponentiation for RSA Encryption

Modular exponentiation is the basis needed to perform RSA encryption and decryption. Execution of 4096-bit modular exponentiation using an embedded system requires many arithmetic operations. This work aims to improve the performance of modular exponentiation for an existing FPGA platform containing a soft core RISC-V processor. The solution is...

Faster than the Speed of Life: Accelerating Developmental Biology Simulations with GPUs and FPGAs

Life scientists are faced with the tough challenge of developing high-performance computer simulations of their increasingly complex models. BioDynaMo is an open-source biological simulation platform that aims to alleviate them from the intricacies that go into development. Life scientists are able to base their models on top of BioDynaMo’s...

Low-Cost Smith-Waterman Acceleration

Due to advancing technology, genetic sequencing has become cheaper over the years. This has caused the demand for computational power to grow even faster than Moore's law. To remedy this problem, we analyzed low-cost hardware solutions to parallelize the computational part of the genetic sequencing. We proposed a novel method for calculating the...

Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option...