Evaluation Framework for Task Scheduling Algorithms in Distributed Reconfigurable Systems

In this dissertation, we propose the design of a simulation framework to investigate the performance of reconfigurable processors in distributed systems. The framework incorporates the partial reconfigurable functionality of the reconfigurable nodes. Depending on the available reconfigurable area, each node is able to execute more than one task...

Quantitative hardware prediction modeling for hardware/software co-design

Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity metrics and hardware characteristics. The resulting...

Efficient Runtime Management of Reconfigurable Hardware Resources

Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford some additional costs compared to hardwired...

K-loops: Loop Transformations for Reconfigurable Architectures

The focus of this dissertation is on kernel loops (K-loops), which are loop nests that contain hardware mapped kernels in the loop body. In this thesis, we propose methods for improving the performance of such K-loops, by using standard loop transformations for exposing and exploiting the coarse grain loop level parallelism. We target a...

Recursive variable expansion: A transformation for reconfigurable computing

Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPGAs, is increasingly used for high-performance computing where massive fine-grain parallelism and pipelining can be exploited. A challenge is to exploit such massive parallelism on FPGAs and more specifically how to map an application on the...

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable systems. This overhead can be reduced by merging multiple data flow graphs representing different kernels of the original program into a single (merged) datapath that will be configured less often compared to the separate datapaths scenario. However,...

Reconfigurable network processing platforms

This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network processing platform targets mainly access, edge,...

Arithmetic soft-core accelerators

In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten's and two's complement notations. The main design goal is to collapse multiple complex arithmetic operations into a single, universal arithmetic unit,...

Scalable Multigigabit Pattern Matching for Packet Inspection

In this paper, we consider hardware-based scanning and analyzing packets payload in order to detect hazardous contents.We present two pattern matching techniques to compare incoming packets against intrusion detection search patterns. The first approach, decoded partial CAM (DpCAM), predecodes incoming characters, aligns the decoded data, and...

The Molen Polymorphic Media Processor

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The proposed media Molen prototype is implemented on...