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Kulkarni, Anurag (author)
The ρ-VEX is a dynamically reconfigurable VLIW processor, developed at TU Delft, which is capable of extracting large amounts of parallelism from applications running on it. However, without a dedicated software layer to dictate the reconfigurations, the ρ-VEX has to depend on another processor to carry out its reconfigurations meaningfully....
master thesis 2018
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Saleem, Muhammad Usman (author)
Over the past many years, technology scaling has resulted in a continuous reduction of lateral and vertical dimensions of transistors. The technology scaling, on the one hand, has led to a commensurate performance gain for very-large-scale integration (VLSI) circuits, but on the other hand, has also made such circuits more vulnerable to ionizing...
master thesis 2018
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Hoozemans, J.J. (author)
Embedded systems range from very simple devices, such as a digital watch, to highly complex systems such as smartphones. In these complex devices, an increasing number of applications need to be executed on a computing platform. Moreover, the number of applications (or programs) usually exceeds the number of processors found on such platforms....
doctoral thesis 2018
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van Bremen, Lennart (author)
The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.<br/>A fully automatic scripted flow is described, constructing an...
master thesis 2017
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Yanik, K.I.M. (author)
The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...
master thesis 2016
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Van Straten, J. (author)
This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...
student report 2016
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Johansen, J. (author)
The ?-VEX is a run-time reconfigurable Very Long Instruction Word (VLIW) processor. This unique processor allows separation of its issue lanes to form independently operating processing cores. Switching between these configuration during run-time allows optimizing the platform for the task(s) it is performing. Porting an Operating System (OS) to...
master thesis 2016
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Meun, K. (author)
Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a...
master thesis 2015
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Iorga, D. (author)
Numerous applications from autonomous vehicles to surveillance systems can benefit from "seeing in 3D". A crucial element of sight is depth detection since this enables evaluation of position and shape. The depth at which objects are located can be estimated by using two or more cameras and comparing the resulting images. Despite the increasing...
master thesis 2015
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Andronikidis, G. (author)
Embedded Reconfigurable Architectures (ERA) is a project with the objective to design a platform that combines reconfigurable computing and network elements which can adapt on-the-fly their composition, organization and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given...
master thesis 2014
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Reda, M.B. (author)
The ?-VEX processor is a parameterized reconfigurable Very Large Instruction Word (VLIW) softcore processor. It can be reconfigured in the issue-width, number and type of functional units (FUs), width of memory buses and number of registers in the multi- ported register file. The current design of the ?-VEX processor supports single cluster...
master thesis 2014
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Nadeem, M. (author)
doctoral thesis 2014
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Hoozemans, J.J. (author)
This thesis describes the design and implementation of an FPGA-based hardware platform based on the rVEX VLIW softcore and the adaption of a Linux 2.0 no_mmu kernel to run on that platform. The rVEX is a runtime reconfigurable VLIW softcore processor. It supports various configurations that allow programs to run faster or more efficient. The...
master thesis 2014
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Anjam, F. (author)
In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organization can be adapted to the specific requirements...
doctoral thesis 2013
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Vahedi, M. (author)
Instruction scheduling aims to reorder instructions in such a way that it covers the delay between an instruction and its dependent successor(s). As a result, the length of schedules are shortened while the processor utilisation increases. This is accomplished by exploiting Instruction Level Parallelism (ILP). The rearrangements made by...
master thesis 2013
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Shankar, A. (author)
A clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this...
master thesis 2013
document
Okmen, Y. (author)
In the last decade, the importance of graphics capabilities have become very important in the mobile market. As a result low power embedded solutions for mobile devices have been eveloped to run computationally intensive graphics applications, which extensively uses floating point calculations. The work proposed in this thesis target the...
master thesis 2011
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Purba, M.S.B. (author), Yigit, E. (author), Regeer, A.J.J. (author)
Deze scriptie beschrijft het ontwerp van een embedded systeem dat de kenmerkende eigenschappen uit de afbeelding van een vingerafdruk haalt. Het betreft een hardware/software codesign, waarbij een VLIW-processor als accelerator is gebruikt.
bachelor thesis 2011
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De Zeeuw, M. (author)
Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a result the performance gap of processors build on FPGA technology compared to Semi-custom ASIC technology is decreasing. The down side of...
master thesis 2011
document
Van den Broeke, G. (author), Mul, D.P.N. (author)
Deze scriptie betreft een onderzoek naar het versnellen van een JPEG-decoder in een embedded systeem. Hierbij wordt de ?-VEX VLIW-processor als accelerator gebruikt. Onderzocht wordt hoe de hardware en software aan elkaar kunnen worden aangepast om de applicatie zo snel mogelijk uit te voeren.
bachelor thesis 2011
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