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Collection: research
(1 - 20 of 23)
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Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Device-Aware Test for Back-Hopping Defects in STT-MRAMs
Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs
Online Fault Detection and Diagnosis in RRAM
Device Aware Diagnosis for Unique Defects in STT-MRAMs
Dependability of Future Edge-AI Processors: Pandora’s Box
Device-Aware Test for Ion Depletion Defects in RRAMs
Characterization and Test of Intermittent Over RESET in RRAMs
Structured Test Development Approach for Computation-in-Memory Architectures
Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs
Hierarchical Memory Diagnosis
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT
PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory
Using Hopfield Networks to Correct Instruction Faults
Recent Trends and Perspectives on Defect-Oriented Testing
Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs
Intermittent Undefined State Fault in RRAMs
Improving the Detection of Undefined State Faults in FinFET SRAMs
Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level
A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs
Collection: research
(1 - 20 of 23)
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2
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