Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS

Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS

Riemens, D.P.

Strydis, C. (mentor)
Gaydadjiev, G.N. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

2010-10-28

Modern applications demand extremely low power budgets in computer architectures for battery-operated devices. In the particular case of implantable devices —the main focus of this thesis— the system must have a long life span and batteries may not be possible or easy to recharge. In addition to power, chip area is also of major concern in this specific scenario. Since implantable devices are sometimes placed at locations inside the body where limited space is available, the implant must be as small as possible. The vast amount of volume of an implant is typically occupied by the battery and its electrodes, so the affordable chip area is very limited. Another reason why we want very small processor cores, is because this approach leaves more space for cache memory and it statistically reduces the chance of hardware failures. In this thesis we focus on the arithmetic unit (AU) of such a core, which is typically the adder/subtracter. The goal is to explore existing fault-tolerant and low-power AUs which are suitable for implementation in biomedical implants. A second objective is to study our own idea for a resource-constrained AU, based on graceful degradation: the so-called scalable arithmetic unit (ScAU). When an error occurs, the ScAU is able to proceed with the computational work, but no longer at the normal throughput: instead of single-cycle we downgrade to double-cycle operations. The design of our ScAU as well as several reference designs are all implemented in VHDL, synthesized and analyzed using Synopsys Design Compiler/PrimeTime and ModelSim. A major part of this thesis is dedicated to fault-tolerant design. An extensive study among common and less frequently employed error-detection schemes is performed. Finally, an error-detection scheme is chosen, applied to the ScAU, as well as to the reference designs for providing fair comparisons. A simple error-correction scheme is implemented as well. The fault-tolerant ScAU proves to have some very interesting advantages over the current state of the art. The fault-tolerant ScAU saves 17% of area, with a speedup of 12% for a 7.3% increase in power consumption, compared to the conventional technique with the lowest costs. Because of these savings, the power-delay-area product reduces by almost 21%. Under specific circumstances, our fault-tolerant ScAU is even capable of saving both area and power.

low-power design
fault tolerant design
computer arithmetic
ASIC
adders
implants

http://resolver.tudelft.nl/uuid:8c8e1930-31b4-4e68-85cd-e6e4ba49f4f2

2010-10-29

Student theses

master thesis

(c) 2010 Riemens, D.P.